From 8a7fc959eb91f4003dac20bcc66d93445f341ddd Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Tue, 4 May 2021 15:21:01 -0400
Subject: [PATCH] small synthesis fixes

---
 wally-pipelined/src/ebu/ahblite.sv | 2 +-
 wally-pipelined/src/ieu/extend.sv  | 2 +-
 wally-pipelined/src/mmu/decoder.sv | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 29bdd7bb..b6103400 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 package ahbliteState;
-  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
+  typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
 endpackage
 
 module ahblite (
diff --git a/wally-pipelined/src/ieu/extend.sv b/wally-pipelined/src/ieu/extend.sv
index 8d79b0a3..e1307537 100644
--- a/wally-pipelined/src/ieu/extend.sv
+++ b/wally-pipelined/src/ieu/extend.sv
@@ -30,7 +30,7 @@ module extend (
   input  logic [2:0]        ImmSrcD,
   output logic [`XLEN-1:0 ] ExtImmD);
 
-  logic [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
+  localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
  
   generate
     always_comb
diff --git a/wally-pipelined/src/mmu/decoder.sv b/wally-pipelined/src/mmu/decoder.sv
index 0d34df7a..2e5dedf2 100644
--- a/wally-pipelined/src/mmu/decoder.sv
+++ b/wally-pipelined/src/mmu/decoder.sv
@@ -31,6 +31,7 @@ module decoder #(parameter BINARY_BITS = 3) (
 );
 
   // *** Double check whether this synthesizes as expected
+  //     -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
   assign one_hot = 1 << binary;
 
 endmodule