Added rem/div operation to postprocessor

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -79,5 +79,8 @@ module fdivsqrt(
     .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
     .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
     .DivBusy);
-  fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM);
+  fdivsqrtpostproc fdivsqrtpostproc(
+    .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
+    .SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
+    .QmM, .WZero, .DivSM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -31,13 +31,14 @@
 `include "wally-config.vh"
 
 module fdivsqrtpostproc(
-  input logic [`DIVb+3:0] WS, WC,
-  input logic [`DIVN-2:0]  D, // U0.N-1
-  input logic [`DIVb:0] FirstU, FirstUM, 
-  input logic [`DIVb+1:0] FirstC,
-  input logic  Firstun,
-  input logic SqrtM,
-  input logic SpecialCaseM,
+  input  logic [`DIVb+3:0] WS, WC,
+  input  logic [`DIVN-2:0]  D, // U0.N-1
+  input  logic [`DIVb:0] FirstU, FirstUM, 
+  input  logic [`DIVb+1:0] FirstC,
+  input  logic  Firstun,
+  input  logic SqrtM,
+  input  logic SpecialCaseM,
+  input  logic remOp,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM