From 890b26466f7fba06f1b08d0090945f8319380834 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Wed, 2 Nov 2022 17:49:40 +0000
Subject: [PATCH] Added rem/div operation to postprocessor

---
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv         |  5 ++++-
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 15 ++++++++-------
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index cde357bf..b992a0d8 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -79,5 +79,8 @@ module fdivsqrt(
     .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
     .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
     .DivBusy);
-  fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM);
+  fdivsqrtpostproc fdivsqrtpostproc(
+    .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
+    .SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
+    .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index e0acd0ed..4600dfbd 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -31,13 +31,14 @@
 `include "wally-config.vh"
 
 module fdivsqrtpostproc(
-  input logic [`DIVb+3:0] WS, WC,
-  input logic [`DIVN-2:0]  D, // U0.N-1
-  input logic [`DIVb:0] FirstU, FirstUM, 
-  input logic [`DIVb+1:0] FirstC,
-  input logic  Firstun,
-  input logic SqrtM,
-  input logic SpecialCaseM,
+  input  logic [`DIVb+3:0] WS, WC,
+  input  logic [`DIVN-2:0]  D, // U0.N-1
+  input  logic [`DIVb:0] FirstU, FirstUM, 
+  input  logic [`DIVb+1:0] FirstC,
+  input  logic  Firstun,
+  input  logic SqrtM,
+  input  logic SpecialCaseM,
+  input  logic remOp,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM