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attempt no 1: just change out x28s for x31s

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bracker 2021-06-11 12:39:28 -05:00
parent 49b5fa3994
commit 8794bf1afa
6 changed files with 18 additions and 18 deletions
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6
wally-pipelined/testgen/privileged/testgen-CAUSE.py
View File

@ -503,9 +503,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u": if fromMode == "s" or fromMode == "u":
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, mstatus, x1 csrrc x31, mstatus, x1
li x1, 0b0100000000000 li x1, 0b0100000000000
csrrs x28, mstatus, x1 csrrs x31, mstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction addi x1, x1, 16 # x1 is now right after the mret instruction
@ -520,7 +520,7 @@ for xlen in xlens:
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, sstatus, x1 csrrc x31, sstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction addi x1, x1, 16 # x1 is now right after the sret instruction

4
wally-pipelined/testgen/privileged/testgen-DELEG.py
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@ -233,9 +233,9 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
{beforeTest} {beforeTest}
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, {testMode}status, x1 csrrc x31, {testMode}status, x1
li x1, 0b{"01" if mode == "s" else "00"}00000000000 li x1, 0b{"01" if mode == "s" else "00"}00000000000
csrrs x28, {testMode}status, x1 csrrs x31, {testMode}status, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the ret instruction addi x1, x1, 16 # x1 is now right after the ret instruction

6
wally-pipelined/testgen/privileged/testgen-EPC.py
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@ -210,9 +210,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u": if fromMode == "s" or fromMode == "u":
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, mstatus, x1 csrrc x31, mstatus, x1
li x1, 0b0100000000000 li x1, 0b0100000000000
csrrs x28, mstatus, x1 csrrs x31, mstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction addi x1, x1, 16 # x1 is now right after the mret instruction
@ -226,7 +226,7 @@ for xlen in xlens:
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, sstatus, x1 csrrc x31, sstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction addi x1, x1, 16 # x1 is now right after the sret instruction

4
wally-pipelined/testgen/privileged/testgen-IE.py
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@ -346,9 +346,9 @@ for xlen in xlens:
# bring down to supervisor mode # bring down to supervisor mode
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, mstatus, x1 csrrc x31, mstatus, x1
li x1, 0b0100000000000 li x1, 0b0100000000000
csrrs x28, mstatus, x1 csrrs x31, mstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction addi x1, x1, 16 # x1 is now right after the mret instruction

6
wally-pipelined/testgen/privileged/testgen-TVAL.py
View File

@ -304,9 +304,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u": if fromMode == "s" or fromMode == "u":
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, mstatus, x1 csrrc x31, mstatus, x1
li x1, 0b0100000000000 li x1, 0b0100000000000
csrrs x28, mstatus, x1 csrrs x31, mstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction addi x1, x1, 16 # x1 is now right after the mret instruction
@ -321,7 +321,7 @@ for xlen in xlens:
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, sstatus, x1 csrrc x31, sstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction addi x1, x1, 16 # x1 is now right after the sret instruction

6
wally-pipelined/testgen/privileged/testgen-TVEC.py
View File

@ -406,9 +406,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u": if fromMode == "s" or fromMode == "u":
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, mstatus, x1 csrrc x31, mstatus, x1
li x1, 0b0100000000000 li x1, 0b0100000000000
csrrs x28, mstatus, x1 csrrs x31, mstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction addi x1, x1, 16 # x1 is now right after the mret instruction
@ -423,7 +423,7 @@ for xlen in xlens:
lines += f""" lines += f"""
li x1, 0b110000000000 li x1, 0b110000000000
csrrc x28, sstatus, x1 csrrc x31, sstatus, x1
auipc x1, 0 auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction addi x1, x1, 16 # x1 is now right after the sret instruction