From 8794bf1afaa1f1cde0df3a280cbd9f81317bc2b2 Mon Sep 17 00:00:00 2001 From: bracker Date: Fri, 11 Jun 2021 12:39:28 -0500 Subject: [PATCH] attempt no 1: just change out x28s for x31s --- wally-pipelined/testgen/privileged/testgen-CAUSE.py | 8 ++++---- wally-pipelined/testgen/privileged/testgen-DELEG.py | 4 ++-- wally-pipelined/testgen/privileged/testgen-EPC.py | 8 ++++---- wally-pipelined/testgen/privileged/testgen-IE.py | 4 ++-- wally-pipelined/testgen/privileged/testgen-TVAL.py | 6 +++--- wally-pipelined/testgen/privileged/testgen-TVEC.py | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 409564f7..0bca336c 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -503,9 +503,9 @@ for xlen in xlens: if fromMode == "s" or fromMode == "u": lines += f""" li x1, 0b110000000000 - csrrc x28, mstatus, x1 + csrrc x31, mstatus, x1 li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrrs x31, mstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the mret instruction @@ -520,7 +520,7 @@ for xlen in xlens: lines += f""" li x1, 0b110000000000 - csrrc x28, sstatus, x1 + csrrc x31, sstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the sret instruction @@ -567,4 +567,4 @@ for xlen in xlens: lines = lines + "\nRV_COMPLIANCE_DATA_END\n" f.write(lines) f.close() - r.close() \ No newline at end of file + r.close() diff --git a/wally-pipelined/testgen/privileged/testgen-DELEG.py b/wally-pipelined/testgen/privileged/testgen-DELEG.py index 4eecb53b..ab08d09d 100644 --- a/wally-pipelined/testgen/privileged/testgen-DELEG.py +++ b/wally-pipelined/testgen/privileged/testgen-DELEG.py @@ -233,9 +233,9 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""): {beforeTest} li x1, 0b110000000000 - csrrc x28, {testMode}status, x1 + csrrc x31, {testMode}status, x1 li x1, 0b{"01" if mode == "s" else "00"}00000000000 - csrrs x28, {testMode}status, x1 + csrrs x31, {testMode}status, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the ret instruction diff --git a/wally-pipelined/testgen/privileged/testgen-EPC.py b/wally-pipelined/testgen/privileged/testgen-EPC.py index 2fd0593b..8093ef40 100644 --- a/wally-pipelined/testgen/privileged/testgen-EPC.py +++ b/wally-pipelined/testgen/privileged/testgen-EPC.py @@ -210,9 +210,9 @@ for xlen in xlens: if fromMode == "s" or fromMode == "u": lines += f""" li x1, 0b110000000000 - csrrc x28, mstatus, x1 + csrrc x31, mstatus, x1 li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrrs x31, mstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the mret instruction @@ -226,7 +226,7 @@ for xlen in xlens: lines += f""" li x1, 0b110000000000 - csrrc x28, sstatus, x1 + csrrc x31, sstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the sret instruction @@ -260,4 +260,4 @@ for xlen in xlens: lines = lines + "\nRV_COMPLIANCE_DATA_END\n" f.write(lines) f.close() - r.close() \ No newline at end of file + r.close() diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/wally-pipelined/testgen/privileged/testgen-IE.py index bb1ecd2c..5a82d019 100644 --- a/wally-pipelined/testgen/privileged/testgen-IE.py +++ b/wally-pipelined/testgen/privileged/testgen-IE.py @@ -346,9 +346,9 @@ for xlen in xlens: # bring down to supervisor mode lines += f""" li x1, 0b110000000000 - csrrc x28, mstatus, x1 + csrrc x31, mstatus, x1 li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrrs x31, mstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the mret instruction diff --git a/wally-pipelined/testgen/privileged/testgen-TVAL.py b/wally-pipelined/testgen/privileged/testgen-TVAL.py index 8a728f7a..572d930c 100644 --- a/wally-pipelined/testgen/privileged/testgen-TVAL.py +++ b/wally-pipelined/testgen/privileged/testgen-TVAL.py @@ -304,9 +304,9 @@ for xlen in xlens: if fromMode == "s" or fromMode == "u": lines += f""" li x1, 0b110000000000 - csrrc x28, mstatus, x1 + csrrc x31, mstatus, x1 li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrrs x31, mstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the mret instruction @@ -321,7 +321,7 @@ for xlen in xlens: lines += f""" li x1, 0b110000000000 - csrrc x28, sstatus, x1 + csrrc x31, sstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the sret instruction diff --git a/wally-pipelined/testgen/privileged/testgen-TVEC.py b/wally-pipelined/testgen/privileged/testgen-TVEC.py index 8b731be8..fcdc80d7 100644 --- a/wally-pipelined/testgen/privileged/testgen-TVEC.py +++ b/wally-pipelined/testgen/privileged/testgen-TVEC.py @@ -406,9 +406,9 @@ for xlen in xlens: if fromMode == "s" or fromMode == "u": lines += f""" li x1, 0b110000000000 - csrrc x28, mstatus, x1 + csrrc x31, mstatus, x1 li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrrs x31, mstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the mret instruction @@ -423,7 +423,7 @@ for xlen in xlens: lines += f""" li x1, 0b110000000000 - csrrc x28, sstatus, x1 + csrrc x31, sstatus, x1 auipc x1, 0 addi x1, x1, 16 # x1 is now right after the sret instruction