From 856ac24686e71dd2e9bf0c4106a1e542c0ad03b2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 24 Jul 2022 00:34:11 -0500 Subject: [PATCH] Removed replay from the config files. --- pipelined/config/buildroot/wally-config.vh | 1 - pipelined/config/fpga/wally-config.vh | 1 - pipelined/config/rv32e/wally-config.vh | 1 - pipelined/config/rv32gc/wally-config.vh | 1 - pipelined/config/rv32i/wally-config.vh | 2 - pipelined/config/rv32ic/wally-config.vh | 2 - pipelined/config/rv64BP/wally-config.vh | 2 - pipelined/config/rv64fp/wally-config.vh | 1 - pipelined/config/rv64fpquad/wally-config.vh | 1 - pipelined/config/rv64gc/wally-config.vh | 1 - pipelined/config/rv64i/wally-config.vh | 1 - pipelined/config/rv64ic/wally-config.vh | 1 - pipelined/regression/wally-pipelined.do | 2 +- pipelined/src/cache/cachefsm.sv | 45 +++++++++++---------- 14 files changed, 24 insertions(+), 38 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index f11b71c0..383cab5b 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -130,5 +130,4 @@ `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 12e9fb36..2d349c8d 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -141,5 +141,4 @@ `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 7d083f3b..4160957b 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -135,5 +135,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 70124d55..f15f15a3 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -133,5 +133,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index d44072d6..001157a1 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -135,6 +135,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index e42fd310..4fcffd73 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -133,6 +133,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 3bc745eb..53ca026c 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -136,6 +136,4 @@ `define TESTSBP 1 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index cc8d1b2b..bf0831d1 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -137,5 +137,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 0dee000e..eb8b0266 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -136,5 +136,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 9afa1a67..19750d6b 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -136,5 +136,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 67ca51a7..99c70cd6 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -136,5 +136,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index fca1f260..a31a555a 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -136,5 +136,4 @@ `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index 6ef601f5..38131139 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -38,7 +38,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 #-- Run the Simulation - run -all + #run -all add log -recursive /* do linux-wave.do run -all diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 7591a512..9d077837 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -131,29 +131,31 @@ module cachefsm always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY; - else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // fetch first, then eviction is necessary. see delay in lru read/write path. - else NextState = STATE_READY; - STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE; + STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY; + else if(DoFlush) NextState = STATE_FLUSH; + // Delayed LRU update. Cannot check if victim line is dirty on this cycle. + // To optimize do the fetch first, then eviction if necessary. + else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; + else NextState = STATE_READY; + STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE; else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY_START; - else NextState = STATE_MISS_FETCH_WDV; - STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; // cpu_busy not needed. load misses have the property of reading from the bus buffer rather than sram. - STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; - else NextState = STATE_MISS_EVICT_DIRTY; - STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. - STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; - else if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; + else NextState = STATE_MISS_FETCH_WDV; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + else NextState = STATE_MISS_EVICT_DIRTY; + STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. + STATE_FLUSH: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + else if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; STATE_FLUSH_WRITE_BACK: if(CacheBusAck) begin - if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - end else NextState = STATE_FLUSH_WRITE_BACK; - default: NextState = STATE_READY; + if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + end else NextState = STATE_FLUSH_WRITE_BACK; + default: NextState = STATE_READY; endcase end @@ -198,7 +200,6 @@ module cachefsm assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. // use the raw requests as we don't want IgnoreRequestTrapM in the critical path (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed - (CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_READY & (DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_EVICT_DIRTY) |