From 81ec1ac858c03b538f12709010f8d3aceec67803 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Aug 2022 04:26:14 -0700 Subject: [PATCH] Separated out radix 2 and radix 4 stages into different modules --- pipelined/regression/wave-fpu.do | 8 +-- pipelined/src/fpu/fdivsqrtiter.sv | 91 +++-------------------------- pipelined/src/fpu/fdivsqrtstage2.sv | 76 ++++++++++++++++++++++++ pipelined/src/fpu/fdivsqrtstage4.sv | 84 ++++++++++++++++++++++++++ 4 files changed, 173 insertions(+), 86 deletions(-) create mode 100644 pipelined/src/fpu/fdivsqrtstage2.sv create mode 100644 pipelined/src/fpu/fdivsqrtstage4.sv diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index 7669c021..cb2622b4 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -29,10 +29,10 @@ add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/otfc/otfc2/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/qsel/qsel2/* -# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/genblk1/qsel4/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/qsel/qsel2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/fdivsqrtstage/stage/genblk1/qsel4/* add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/* add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/* add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/* diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv index daae52cc..bd336fc4 100644 --- a/pipelined/src/fpu/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrtiter.sv @@ -122,9 +122,15 @@ module fdivsqrtiter( genvar i; generate for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations - divinteration divinteration(.D, .DBar, .D2, .DBar2, .SqrtM, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), - .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + if (`RADIX == 2) begin: stage + fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), + .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + end else begin: stage + fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), + .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i])); + end if(i<(`DIVCOPIES-1)) begin if (`RADIX==2)begin assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0}; @@ -174,84 +180,5 @@ module fdivsqrtiter( assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0}; else assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0}; - - endmodule -//////////////// -// Submodules // -//////////////// - - /* verilator lint_off UNOPTFLAT */ -module divinteration ( - input logic [`DIVN-2:0] D, - input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] Q, QM, - input logic [`DIVb:0] S, SM, - input logic [`DIVb+3:0] WS, WC, - input logic [`DIVb-1:0] C, - input logic SqrtM, - output logic [`DIVb:0] QNext, QMNext, - output logic qn, - output logic [`DIVb:0] SNext, SMNext, - output logic [`DIVb+3:0] WSA, WCA -); - /* verilator lint_on UNOPTFLAT */ - - logic [`DIVb+3:0] Dsel; - logic [3:0] q; - logic qp, qz; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - - // Qmient Selection logic - // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) - // q encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 - if(`RADIX == 2) begin : qsel - qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); - fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F); - end else begin - qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q); - // fgen4 fgen4(.s(q), .C, .S, .SM, .F); - end - - if(`RADIX == 2) begin : dsel - assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); - end else begin - always_comb - case (q) - 4'b1000: Dsel = DBar2; - 4'b0100: Dsel = DBar; - 4'b0000: Dsel = '0; - 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; - 4'b0001: Dsel = D2; - default: Dsel = 'x; - endcase - end - // Partial Product Generation - // WSA, WCA = WS + WC - qD - assign AddIn = SqrtM ? F : Dsel; - if (`RADIX == 2) begin : csa - csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); - end else begin - csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); - end - - if (`RADIX == 2) begin : otfc - otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); - sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext); - end else begin - otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); - // sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); - end - -endmodule - - - - diff --git a/pipelined/src/fpu/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrtstage2.sv new file mode 100644 index 00000000..9654be84 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtstage2.sv @@ -0,0 +1,76 @@ +/////////////////////////////////////////// +// fdivsqrtstage2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/* verilator lint_off UNOPTFLAT */ +module fdivsqrtstage2 ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] Q, QM, + input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb-1:0] C, + input logic SqrtM, + output logic [`DIVb:0] QNext, QMNext, + output logic qn, + output logic [`DIVb:0] SNext, SMNext, + output logic [`DIVb+3:0] WSA, WCA +); + /* verilator lint_on UNOPTFLAT */ + + logic [`DIVb+3:0] Dsel; + logic qp, qz; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + + // Qmient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // q encoding: + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 + qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); + fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F); + + assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); + // Partial Product Generation + // WSA, WCA = WS + WC - qD + assign AddIn = SqrtM ? F : Dsel; + csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); + + // *** dh 8/29/22: will need to trim down to just sotfc + otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); + sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext); +endmodule + + diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv new file mode 100644 index 00000000..1da37b0c --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtstage4.sv @@ -0,0 +1,84 @@ +/////////////////////////////////////////// +// fdivsqrtstage4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/* verilator lint_off UNOPTFLAT */ +module fdivsqrtstage4 ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] Q, QM, + input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb-1:0] C, + input logic SqrtM, + output logic [`DIVb:0] QNext, QMNext, + output logic qn, + output logic [`DIVb:0] SNext, SMNext, + output logic [`DIVb+3:0] WSA, WCA +); + /* verilator lint_on UNOPTFLAT */ + + logic [`DIVb+3:0] Dsel; + logic [3:0] q; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + + // Qmient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // q encoding: + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 + qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q); + // fgen4 fgen4(.s(q), .C, .S, .SM, .F); + + always_comb + case (q) + 4'b1000: Dsel = DBar2; + 4'b0100: Dsel = DBar; + 4'b0000: Dsel = '0; + 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; + 4'b0001: Dsel = D2; + default: Dsel = 'x; + endcase + + // Partial Product Generation + // WSA, WCA = WS + WC - qD + assign AddIn = SqrtM ? F : Dsel; + csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); + + otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); + // sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); +endmodule + +