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Added ASID & Global PTE handling to TLB CAM

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This commit is contained in:
David Harris 2021-07-04 17:52:00 -04:00
parent 07ef67e537
commit 80666f0a71
19 changed files with 87 additions and 125 deletions
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4
wally-pipelined/config/buildroot/wally-config.vh
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@ -49,8 +49,8 @@
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16

4
wally-pipelined/config/busybear/wally-config.vh
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@ -50,8 +50,8 @@
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16

4
wally-pipelined/config/coremark/wally-config.vh
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@ -49,8 +49,8 @@
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Address space
`define RESET_VECTOR 64'h00000000000100b0

4
wally-pipelined/config/coremark_bare/wally-config.vh
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@ -49,8 +49,8 @@
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16

4
wally-pipelined/config/rv32ic/wally-config.vh
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@ -48,8 +48,8 @@
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16

4
wally-pipelined/config/rv64BP/wally-config.vh
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@ -50,8 +50,8 @@
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Address space
`define RESET_VECTOR 64'h0000000000000000

4
wally-pipelined/config/rv64ic/wally-config.vh
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@ -49,8 +49,8 @@
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64

4
wally-pipelined/config/rv64icfd/wally-config.vh
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@ -49,8 +49,8 @@
`define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16

4
wally-pipelined/config/rv64imc/wally-config.vh
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@ -48,8 +48,8 @@
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Address space
`define RESET_VECTOR 64'h0000000080000000

4
wally-pipelined/config/shared/wally-constants.vh
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@ -39,7 +39,9 @@
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
`define PPN_BITS (`XLEN==32 ? 22 : 44)
`define PA_BITS (`XLEN==32 ? 34 : 56)
`define SVMODE_BITS (`XLEN == 32 ? 1 : 4)
`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
`define ASID_BASE (`XLEN==32 ? 22 : 44)
`define ASID_BITS (`XLEN==32 ? 9 : 16)
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec

2
wally-pipelined/src/ifu/ifu.sv
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@ -116,7 +116,7 @@ module ifu (
end
endgenerate
mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1))
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
itlb(.TLBAccessType(2'b10),
.VirtualAddress(PCF),
.Size(2'b10),

2
wally-pipelined/src/lsu/lsu.sv
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@ -124,7 +124,7 @@ module lsu (
// CPU's read data input ReadDataW.
assign ReadDataW = HRDATAW;
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0))
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.TLBAccessType(MemRWM),
.VirtualAddress(MemAdrM),
.Size(Funct3M[1:0]),

6
wally-pipelined/src/mmu/mmu.sv
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@ -26,9 +26,7 @@
`include "wally-config.vh"
// The TLB will have 2**ENTRY_BITS total entries
module mmu #(parameter ENTRY_BITS = 3,
module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
parameter IMMU = 0) (
input logic clk, reset,
@ -83,7 +81,7 @@ module mmu #(parameter ENTRY_BITS = 3,
logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
// Translation lookaside buffer
tlb #(.ENTRY_BITS(ENTRY_BITS), .ITLB(IMMU)) tlb(.*);
tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(.*);
///////////////////////////////////////////
// Check physical memory accesses

30
wally-pipelined/src/mmu/tlb.sv
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@ -49,7 +49,7 @@
`include "wally-config.vh"
// The TLB will have 2**ENTRY_BITS total entries
module tlb #(parameter ENTRY_BITS = 3,
module tlb #(parameter TLB_ENTRIES = 8,
parameter ITLB = 0) (
input logic clk, reset,
@ -88,8 +88,6 @@ module tlb #(parameter ENTRY_BITS = 3,
output logic TLBPageFault
);
localparam NENTRIES = 2**ENTRY_BITS;
logic Translate;
logic TLBAccess, ReadAccess, WriteAccess;
@ -97,8 +95,7 @@ module tlb #(parameter ENTRY_BITS = 3,
logic [`SVMODE_BITS-1:0] SvMode;
logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
//logic [ENTRY_BITS-1:0] WriteIndex;
logic [NENTRIES-1:0] ReadLines, WriteLines, WriteEnables; // used as the one-hot encoding of WriteIndex
logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, Global; // used as the one-hot encoding of WriteIndex
// Sections of the virtual and physical addresses
logic [`VPN_BITS-1:0] VirtualPageNumber;
@ -110,24 +107,19 @@ module tlb #(parameter ENTRY_BITS = 3,
logic [7:0] PTEAccessBits;
logic [11:0] PageOffset;
// Useful PTE Control Bits
logic PTE_U, PTE_X, PTE_W, PTE_R;
// Pattern location in the CAM and type of page hit
//ogic [ENTRY_BITS-1:0] VPNIndex;
logic PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
logic [1:0] HitPageType;
// Whether the virtual address has a match in the CAM
logic CAMHit;
logic [`ASID_BITS-1:0] ASID;
// Grab the sv mode from SATP and determine whether translation should occur
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign ASID = SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE];
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
// Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
//decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
assign WriteEnables = WriteLines & {(2**ENTRY_BITS){TLBWrite}};
// Determine whether to write TLB
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
// this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,
@ -142,20 +134,18 @@ module tlb #(parameter ENTRY_BITS = 3,
end
endgenerate
// Determine how the TLB is currently being used
// Note that we use ReadAccess for both loads and instruction fetches
assign ReadAccess = TLBAccessType[1];
assign WriteAccess = TLBAccessType[0];
assign TLBAccess = ReadAccess || WriteAccess;
// TLB entries are evicted according to the LRU algorithm
tlblru #(ENTRY_BITS) lru(.*);
tlblru #(TLB_ENTRIES) lru(.*);
// TLB memory
tlbram #(ENTRY_BITS) tlbram(.*);
tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
tlbram #(TLB_ENTRIES) tlbram(.*);
tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
// Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced.

30
wally-pipelined/src/mmu/tlbcam.sv
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@ -28,44 +28,36 @@
`include "wally-config.vh"
module tlbcam #(parameter ENTRY_BITS = 3,
module tlbcam #(parameter TLB_ENTRIES = 8,
parameter KEY_BITS = 20,
parameter SEGMENT_BITS = 10) (
input logic clk, reset,
input logic [KEY_BITS-1:0] VirtualPageNumber,
input logic [`VPN_BITS-1:0] VirtualPageNumber,
input logic [1:0] PageTypeWriteVal,
input logic TLBFlush,
input logic [2**ENTRY_BITS-1:0] WriteEnables,
//output logic [ENTRY_BITS-1:0] VPNIndex,
output logic [2**ENTRY_BITS-1:0] ReadLines,
input logic [TLB_ENTRIES-1:0] WriteEnables,
input logic [TLB_ENTRIES-1:0] Global
input logic [`ASID_BITS-1:0] ASID,
output logic [TLB_ENTRIES-1:0] ReadLines,
output logic [1:0] HitPageType,
output logic CAMHit
);
localparam NENTRIES = 2**ENTRY_BITS;
logic [1:0] PageTypeRead [TLB_ENTRIES-1:0];
logic [TLB_ENTRIES-1:0] Matches;
logic [1:0] PageTypeRead [NENTRIES-1:0];
logic [NENTRIES-1:0] Matches;
// Create NENTRIES CAM lines, each of which will independently consider
// Create TLB_ENTRIES CAM lines, each of which will independently consider
// whether the requested virtual address is a match. Each line stores the
// original virtual page number from when the address was written, regardless
// of page type. However, matches are determined based on a subset of the
// page number segments.
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
.WriteEnable(WriteEnables),
.PageTypeRead, // *** change name to agree
.Match(ReadLines), // *** change name to agree
.*);
// In case there are multiple matches in the CAM, select only one
// *** it might be guaranteed that the CAM will never have multiple matches.
// If so, this is just an encoder
//priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
assign CAMHit = |ReadLines & ~TLBFlush;
assign HitPageType = PageTypeRead.or; // applies OR to elements of the (NENTRIES x 2) array to get 2-bit result
assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result
endmodule

37
wally-pipelined/src/mmu/tlbcamline.sv
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@ -31,28 +31,21 @@
module tlbcamline #(parameter KEY_BITS = 20,
parameter SEGMENT_BITS = 10) (
input logic clk, reset,
// input to check which SvMode is running
// input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
// The requested page number to compare against the key
input logic [KEY_BITS-1:0] VirtualPageNumber,
// Signals to write a new entry to this line
input logic WriteEnable,
input logic [`VPN_BITS-1:0] VirtualPageNumber, // The requested page number to compare against the key
input logic [`ASID_BITS-1:0] ASID,
input logic WriteEnable, // Write a new entry to this line
input logic Global,
input logic [1:0] PageTypeWriteVal,
input logic TLBFlush, // Flush this line (set valid to 0)
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
output logic Match
);
// Flush this line (set valid to 0)
input logic TLBFlush,
// This entry is a key for a tera, giga, mega, or kilopage.
// PageTypeRead is a key for a tera, giga, mega, or kilopage.
// PageType == 2'b00 --> kilopage
// PageType == 2'b01 --> megapage
// PageType == 2'b10 --> gigapage
// PageType == 2'b11 --> terapage
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
output logic Match
);
// This entry has KEY_BITS for the key plus one valid bit.
logic Valid;
@ -60,15 +53,16 @@ module tlbcamline #(parameter KEY_BITS = 20,
logic [1:0] PageType;
// Split up key and query into sections for each page table level.
logic [`ASID_BITS-1:0] Key_ASID;
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
logic Match0, Match1;
logic MatchASID, Match0, Match1;
// *** need to add ASID and G bit support
assign MatchASID = (ASID == Key_ASID) | Global;
generate
if (`XLEN == 32) begin
assign {Key1, Key0} = Key;
assign {Key_ASID, Key1, Key0} = Key;
assign {Query1, Query0} = VirtualPageNumber;
// Calculate the actual match value based on the input vpn and the page type.
@ -84,7 +78,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
logic Match2, Match3;
assign {Query3, Query2, Query1, Query0} = VirtualPageNumber;
assign {Key3, Key2, Key1, Key0} = Key;
assign {Key_ASID, Key3, Key2, Key1, Key0} = Key;
// Calculate the actual match value based on the input vpn and the page type.
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
@ -107,6 +101,5 @@ module tlbcamline #(parameter KEY_BITS = 20,
// *** Might we want to update stored key right away to output match on the
// write cycle? (using a mux)
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, VirtualPageNumber, Key);
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {ASID, VirtualPageNumber}, Key);
endmodule

23
wally-pipelined/src/mmu/tlblru.sv
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@ -24,34 +24,27 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
module tlblru #(parameter ENTRY_BITS = 3) (
module tlblru #(parameter TLB_ENTRIES = 8) (
input logic clk, reset,
input logic TLBWrite,
input logic TLBFlush,
input logic [2**ENTRY_BITS-1:0] ReadLines,
input logic [TLB_ENTRIES-1:0] ReadLines,
input logic CAMHit,
output logic [2**ENTRY_BITS-1:0] WriteLines
output logic [TLB_ENTRIES-1:0] WriteLines
);
localparam NENTRIES = 2**ENTRY_BITS;
// Keep a "recently-used" record for each TLB entry. On access, set to 1
logic [NENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
// One-hot encodings of which line is being accessed
logic [NENTRIES-1:0] AccessLines;
// High if the next access causes all RU bits to be 1
logic AllUsed;
logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
logic AllUsed; // High if the next access causes all RU bits to be 1
// Find the first line not recently used
tlbpriority #(NENTRIES) nru(~RUBits, WriteLines);
tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines);
// Track recently used lines, updating on a CAM Hit or TLB write
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
assign RUBitsAccessed = AccessLines | RUBits;
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
endmodule

1
wally-pipelined/src/mmu/tlbphysicalpagemask.sv
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@ -32,7 +32,6 @@ module tlbphysicalpagemask (
input logic [`VPN_BITS-1:0] VPN,
input logic [`PPN_BITS-1:0] PPN,
input logic [1:0] PageType,
output logic [`PPN_BITS-1:0] MixedPageNumber
);

17
wally-pipelined/src/mmu/tlbram.sv
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@ -27,25 +27,20 @@
`include "wally-config.vh"
module tlbram #(parameter ENTRY_BITS = 3) (
module tlbram #(parameter TLB_ENTRIES = 8) (
input logic clk, reset,
//input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused?
input logic [`XLEN-1:0] PTEWriteVal,
// input logic TLBWrite,
input logic [2**ENTRY_BITS-1:0] ReadLines, WriteEnables,
input logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables,
output logic [`PPN_BITS-1:0] PhysicalPageNumber,
output logic [7:0] PTEAccessBits
output logic [7:0] PTEAccessBits,
output logic [TLB_ENTRIES-1:0] Global
);
localparam NENTRIES = 2**ENTRY_BITS;
logic [`XLEN-1:0] RamRead[NENTRIES-1:0];
logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0];
logic [`XLEN-1:0] PageTableEntry;
// Generate a flop for every entry in the RAM
tlbramline #(`XLEN) tlblineram[NENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
assign PTEAccessBits = PageTableEntry[7:0];