forked from Github_Repos/cvw
Added ASID & Global PTE handling to TLB CAM
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@ -49,8 +49,8 @@
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`define MEM_VIRTMEM 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -50,8 +50,8 @@
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`define MEM_VIRTMEM 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -49,8 +49,8 @@
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`define MEM_VIRTMEM 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Address space
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// Address space
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`define RESET_VECTOR 64'h00000000000100b0
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`define RESET_VECTOR 64'h00000000000100b0
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@ -49,8 +49,8 @@
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -48,8 +48,8 @@
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -50,8 +50,8 @@
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Address space
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// Address space
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`define RESET_VECTOR 64'h0000000000000000
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`define RESET_VECTOR 64'h0000000000000000
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@ -49,8 +49,8 @@
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -49,8 +49,8 @@
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -48,8 +48,8 @@
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`define MEM_VIRTMEM 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRY_BITS 5
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRY_BITS 5
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`define DTLB_ENTRIES 32
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// Address space
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// Address space
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`define RESET_VECTOR 64'h0000000080000000
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`define RESET_VECTOR 64'h0000000080000000
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@ -39,7 +39,9 @@
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`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
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`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
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`define PPN_BITS (`XLEN==32 ? 22 : 44)
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`define PPN_BITS (`XLEN==32 ? 22 : 44)
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`define PA_BITS (`XLEN==32 ? 34 : 56)
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`define PA_BITS (`XLEN==32 ? 34 : 56)
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`define SVMODE_BITS (`XLEN == 32 ? 1 : 4)
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`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
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`define ASID_BASE (`XLEN==32 ? 22 : 44)
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`define ASID_BITS (`XLEN==32 ? 9 : 16)
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// constants to check SATP_MODE against
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// constants to check SATP_MODE against
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// defined in Table 4.3 of the privileged spec
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// defined in Table 4.3 of the privileged spec
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@ -116,7 +116,7 @@ module ifu (
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end
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end
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endgenerate
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endgenerate
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mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1))
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mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
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itlb(.TLBAccessType(2'b10),
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itlb(.TLBAccessType(2'b10),
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.VirtualAddress(PCF),
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.VirtualAddress(PCF),
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.Size(2'b10),
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.Size(2'b10),
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@ -124,7 +124,7 @@ module lsu (
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// CPU's read data input ReadDataW.
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// CPU's read data input ReadDataW.
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assign ReadDataW = HRDATAW;
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assign ReadDataW = HRDATAW;
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mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0))
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.TLBAccessType(MemRWM),
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dmmu(.TLBAccessType(MemRWM),
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.VirtualAddress(MemAdrM),
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.VirtualAddress(MemAdrM),
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.Size(Funct3M[1:0]),
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.Size(Funct3M[1:0]),
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@ -26,9 +26,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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// The TLB will have 2**ENTRY_BITS total entries
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module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
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module mmu #(parameter ENTRY_BITS = 3,
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parameter IMMU = 0) (
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parameter IMMU = 0) (
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input logic clk, reset,
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input logic clk, reset,
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@ -83,7 +81,7 @@ module mmu #(parameter ENTRY_BITS = 3,
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logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
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logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
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// Translation lookaside buffer
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// Translation lookaside buffer
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tlb #(.ENTRY_BITS(ENTRY_BITS), .ITLB(IMMU)) tlb(.*);
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tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(.*);
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Check physical memory accesses
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// Check physical memory accesses
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@ -49,7 +49,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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// The TLB will have 2**ENTRY_BITS total entries
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb #(parameter ENTRY_BITS = 3,
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module tlb #(parameter TLB_ENTRIES = 8,
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parameter ITLB = 0) (
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parameter ITLB = 0) (
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input logic clk, reset,
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input logic clk, reset,
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@ -88,8 +88,6 @@ module tlb #(parameter ENTRY_BITS = 3,
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output logic TLBPageFault
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output logic TLBPageFault
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);
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic Translate;
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logic Translate;
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logic TLBAccess, ReadAccess, WriteAccess;
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logic TLBAccess, ReadAccess, WriteAccess;
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@ -97,8 +95,7 @@ module tlb #(parameter ENTRY_BITS = 3,
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logic [`SVMODE_BITS-1:0] SvMode;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
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logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
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//logic [ENTRY_BITS-1:0] WriteIndex;
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logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, Global; // used as the one-hot encoding of WriteIndex
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logic [NENTRIES-1:0] ReadLines, WriteLines, WriteEnables; // used as the one-hot encoding of WriteIndex
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// Sections of the virtual and physical addresses
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// Sections of the virtual and physical addresses
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logic [`VPN_BITS-1:0] VirtualPageNumber;
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logic [`VPN_BITS-1:0] VirtualPageNumber;
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@ -110,24 +107,19 @@ module tlb #(parameter ENTRY_BITS = 3,
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logic [7:0] PTEAccessBits;
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logic [7:0] PTEAccessBits;
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logic [11:0] PageOffset;
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logic [11:0] PageOffset;
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// Useful PTE Control Bits
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logic PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
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logic PTE_U, PTE_X, PTE_W, PTE_R;
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// Pattern location in the CAM and type of page hit
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//ogic [ENTRY_BITS-1:0] VPNIndex;
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logic [1:0] HitPageType;
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logic [1:0] HitPageType;
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// Whether the virtual address has a match in the CAM
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logic CAMHit;
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logic CAMHit;
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logic [`ASID_BITS-1:0] ASID;
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// Grab the sv mode from SATP and determine whether translation should occur
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// Grab the sv mode from SATP and determine whether translation should occur
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign ASID = SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE];
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assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
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assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
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assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
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assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
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// Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
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// Determine whether to write TLB
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//decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
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assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
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assign WriteEnables = WriteLines & {(2**ENTRY_BITS){TLBWrite}};
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// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
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// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
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// this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,
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// this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,
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@ -142,20 +134,18 @@ module tlb #(parameter ENTRY_BITS = 3,
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end
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end
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endgenerate
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endgenerate
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// Determine how the TLB is currently being used
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// Determine how the TLB is currently being used
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// Note that we use ReadAccess for both loads and instruction fetches
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// Note that we use ReadAccess for both loads and instruction fetches
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assign ReadAccess = TLBAccessType[1];
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assign ReadAccess = TLBAccessType[1];
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assign WriteAccess = TLBAccessType[0];
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assign WriteAccess = TLBAccessType[0];
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assign TLBAccess = ReadAccess || WriteAccess;
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assign TLBAccess = ReadAccess || WriteAccess;
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// TLB entries are evicted according to the LRU algorithm
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// TLB entries are evicted according to the LRU algorithm
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tlblru #(ENTRY_BITS) lru(.*);
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tlblru #(TLB_ENTRIES) lru(.*);
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// TLB memory
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// TLB memory
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tlbram #(ENTRY_BITS) tlbram(.*);
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tlbram #(TLB_ENTRIES) tlbram(.*);
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tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
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tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
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// Replace segments of the virtual page number with segments of the physical
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// Replace segments of the virtual page number with segments of the physical
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// page number. For 4 KB pages, the entire virtual page number is replaced.
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// page number. For 4 KB pages, the entire virtual page number is replaced.
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`include "wally-config.vh"
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`include "wally-config.vh"
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module tlbcam #(parameter ENTRY_BITS = 3,
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module tlbcam #(parameter TLB_ENTRIES = 8,
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parameter KEY_BITS = 20,
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parameter KEY_BITS = 20,
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parameter SEGMENT_BITS = 10) (
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parameter SEGMENT_BITS = 10) (
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input logic clk, reset,
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input logic clk, reset,
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input logic [KEY_BITS-1:0] VirtualPageNumber,
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input logic [`VPN_BITS-1:0] VirtualPageNumber,
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input logic [1:0] PageTypeWriteVal,
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input logic [1:0] PageTypeWriteVal,
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input logic TLBFlush,
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input logic TLBFlush,
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input logic [2**ENTRY_BITS-1:0] WriteEnables,
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input logic [TLB_ENTRIES-1:0] WriteEnables,
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input logic [TLB_ENTRIES-1:0] Global
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//output logic [ENTRY_BITS-1:0] VPNIndex,
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input logic [`ASID_BITS-1:0] ASID,
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output logic [2**ENTRY_BITS-1:0] ReadLines,
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output logic [TLB_ENTRIES-1:0] ReadLines,
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output logic [1:0] HitPageType,
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output logic [1:0] HitPageType,
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output logic CAMHit
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output logic CAMHit
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);
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [1:0] PageTypeRead [TLB_ENTRIES-1:0];
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logic [TLB_ENTRIES-1:0] Matches;
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logic [1:0] PageTypeRead [NENTRIES-1:0];
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// Create TLB_ENTRIES CAM lines, each of which will independently consider
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logic [NENTRIES-1:0] Matches;
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// Create NENTRIES CAM lines, each of which will independently consider
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// whether the requested virtual address is a match. Each line stores the
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// whether the requested virtual address is a match. Each line stores the
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// original virtual page number from when the address was written, regardless
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// original virtual page number from when the address was written, regardless
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// of page type. However, matches are determined based on a subset of the
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// of page type. However, matches are determined based on a subset of the
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// page number segments.
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// page number segments.
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tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
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tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
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.WriteEnable(WriteEnables),
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.WriteEnable(WriteEnables),
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.PageTypeRead, // *** change name to agree
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.PageTypeRead, // *** change name to agree
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.Match(ReadLines), // *** change name to agree
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.Match(ReadLines), // *** change name to agree
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.*);
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.*);
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// In case there are multiple matches in the CAM, select only one
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// *** it might be guaranteed that the CAM will never have multiple matches.
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// If so, this is just an encoder
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//priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
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assign CAMHit = |ReadLines & ~TLBFlush;
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assign CAMHit = |ReadLines & ~TLBFlush;
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assign HitPageType = PageTypeRead.or; // applies OR to elements of the (NENTRIES x 2) array to get 2-bit result
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assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result
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endmodule
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endmodule
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`include "wally-config.vh"
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`include "wally-config.vh"
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module tlbcamline #(parameter KEY_BITS = 20,
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module tlbcamline #(parameter KEY_BITS = 20,
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parameter SEGMENT_BITS = 10) (
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parameter SEGMENT_BITS = 10) (
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input logic clk, reset,
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input logic clk, reset,
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input logic [`VPN_BITS-1:0] VirtualPageNumber, // The requested page number to compare against the key
|
||||||
|
input logic [`ASID_BITS-1:0] ASID,
|
||||||
|
input logic WriteEnable, // Write a new entry to this line
|
||||||
|
input logic Global,
|
||||||
|
input logic [1:0] PageTypeWriteVal,
|
||||||
|
input logic TLBFlush, // Flush this line (set valid to 0)
|
||||||
|
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
|
||||||
|
output logic Match
|
||||||
|
);
|
||||||
|
|
||||||
// input to check which SvMode is running
|
// PageTypeRead is a key for a tera, giga, mega, or kilopage.
|
||||||
// input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
|
|
||||||
|
|
||||||
// The requested page number to compare against the key
|
|
||||||
input logic [KEY_BITS-1:0] VirtualPageNumber,
|
|
||||||
|
|
||||||
// Signals to write a new entry to this line
|
|
||||||
input logic WriteEnable,
|
|
||||||
input logic [1:0] PageTypeWriteVal,
|
|
||||||
|
|
||||||
// Flush this line (set valid to 0)
|
|
||||||
input logic TLBFlush,
|
|
||||||
|
|
||||||
// This entry is a key for a tera, giga, mega, or kilopage.
|
|
||||||
// PageType == 2'b00 --> kilopage
|
// PageType == 2'b00 --> kilopage
|
||||||
// PageType == 2'b01 --> megapage
|
// PageType == 2'b01 --> megapage
|
||||||
// PageType == 2'b10 --> gigapage
|
// PageType == 2'b10 --> gigapage
|
||||||
// PageType == 2'b11 --> terapage
|
// PageType == 2'b11 --> terapage
|
||||||
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
|
|
||||||
output logic Match
|
|
||||||
);
|
|
||||||
|
|
||||||
// This entry has KEY_BITS for the key plus one valid bit.
|
// This entry has KEY_BITS for the key plus one valid bit.
|
||||||
logic Valid;
|
logic Valid;
|
||||||
@ -60,15 +53,16 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
|||||||
logic [1:0] PageType;
|
logic [1:0] PageType;
|
||||||
|
|
||||||
// Split up key and query into sections for each page table level.
|
// Split up key and query into sections for each page table level.
|
||||||
|
logic [`ASID_BITS-1:0] Key_ASID;
|
||||||
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
|
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
|
||||||
logic Match0, Match1;
|
logic MatchASID, Match0, Match1;
|
||||||
|
|
||||||
// *** need to add ASID and G bit support
|
assign MatchASID = (ASID == Key_ASID) | Global;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`XLEN == 32) begin
|
if (`XLEN == 32) begin
|
||||||
|
|
||||||
assign {Key1, Key0} = Key;
|
assign {Key_ASID, Key1, Key0} = Key;
|
||||||
assign {Query1, Query0} = VirtualPageNumber;
|
assign {Query1, Query0} = VirtualPageNumber;
|
||||||
|
|
||||||
// Calculate the actual match value based on the input vpn and the page type.
|
// Calculate the actual match value based on the input vpn and the page type.
|
||||||
@ -84,7 +78,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
|||||||
logic Match2, Match3;
|
logic Match2, Match3;
|
||||||
|
|
||||||
assign {Query3, Query2, Query1, Query0} = VirtualPageNumber;
|
assign {Query3, Query2, Query1, Query0} = VirtualPageNumber;
|
||||||
assign {Key3, Key2, Key1, Key0} = Key;
|
assign {Key_ASID, Key3, Key2, Key1, Key0} = Key;
|
||||||
|
|
||||||
// Calculate the actual match value based on the input vpn and the page type.
|
// Calculate the actual match value based on the input vpn and the page type.
|
||||||
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
|
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
|
||||||
@ -107,6 +101,5 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
|||||||
// *** Might we want to update stored key right away to output match on the
|
// *** Might we want to update stored key right away to output match on the
|
||||||
// write cycle? (using a mux)
|
// write cycle? (using a mux)
|
||||||
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
|
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
|
||||||
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, VirtualPageNumber, Key);
|
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {ASID, VirtualPageNumber}, Key);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -24,34 +24,27 @@
|
|||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
|
|
||||||
module tlblru #(parameter ENTRY_BITS = 3) (
|
module tlblru #(parameter TLB_ENTRIES = 8) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic TLBWrite,
|
input logic TLBWrite,
|
||||||
input logic TLBFlush,
|
input logic TLBFlush,
|
||||||
input logic [2**ENTRY_BITS-1:0] ReadLines,
|
input logic [TLB_ENTRIES-1:0] ReadLines,
|
||||||
input logic CAMHit,
|
input logic CAMHit,
|
||||||
output logic [2**ENTRY_BITS-1:0] WriteLines
|
output logic [TLB_ENTRIES-1:0] WriteLines
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam NENTRIES = 2**ENTRY_BITS;
|
logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
|
||||||
|
logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
|
||||||
// Keep a "recently-used" record for each TLB entry. On access, set to 1
|
logic AllUsed; // High if the next access causes all RU bits to be 1
|
||||||
logic [NENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
|
|
||||||
|
|
||||||
// One-hot encodings of which line is being accessed
|
|
||||||
logic [NENTRIES-1:0] AccessLines;
|
|
||||||
|
|
||||||
// High if the next access causes all RU bits to be 1
|
|
||||||
logic AllUsed;
|
|
||||||
|
|
||||||
// Find the first line not recently used
|
// Find the first line not recently used
|
||||||
tlbpriority #(NENTRIES) nru(~RUBits, WriteLines);
|
tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines);
|
||||||
|
|
||||||
// Track recently used lines, updating on a CAM Hit or TLB write
|
// Track recently used lines, updating on a CAM Hit or TLB write
|
||||||
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
|
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
|
||||||
assign RUBitsAccessed = AccessLines | RUBits;
|
assign RUBitsAccessed = AccessLines | RUBits;
|
||||||
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
|
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
|
||||||
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
|
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
|
||||||
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
|
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -29,10 +29,9 @@
|
|||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module tlbphysicalpagemask (
|
module tlbphysicalpagemask (
|
||||||
input logic [`VPN_BITS-1:0] VPN,
|
input logic [`VPN_BITS-1:0] VPN,
|
||||||
input logic [`PPN_BITS-1:0] PPN,
|
input logic [`PPN_BITS-1:0] PPN,
|
||||||
input logic [1:0] PageType,
|
input logic [1:0] PageType,
|
||||||
|
|
||||||
output logic [`PPN_BITS-1:0] MixedPageNumber
|
output logic [`PPN_BITS-1:0] MixedPageNumber
|
||||||
);
|
);
|
||||||
|
|
||||||
|
@ -27,25 +27,20 @@
|
|||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module tlbram #(parameter ENTRY_BITS = 3) (
|
module tlbram #(parameter TLB_ENTRIES = 8) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
//input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
|
|
||||||
// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused?
|
|
||||||
input logic [`XLEN-1:0] PTEWriteVal,
|
input logic [`XLEN-1:0] PTEWriteVal,
|
||||||
// input logic TLBWrite,
|
input logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables,
|
||||||
input logic [2**ENTRY_BITS-1:0] ReadLines, WriteEnables,
|
|
||||||
|
|
||||||
output logic [`PPN_BITS-1:0] PhysicalPageNumber,
|
output logic [`PPN_BITS-1:0] PhysicalPageNumber,
|
||||||
output logic [7:0] PTEAccessBits
|
output logic [7:0] PTEAccessBits,
|
||||||
|
output logic [TLB_ENTRIES-1:0] Global
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam NENTRIES = 2**ENTRY_BITS;
|
logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0];
|
||||||
|
|
||||||
logic [`XLEN-1:0] RamRead[NENTRIES-1:0];
|
|
||||||
logic [`XLEN-1:0] PageTableEntry;
|
logic [`XLEN-1:0] PageTableEntry;
|
||||||
|
|
||||||
// Generate a flop for every entry in the RAM
|
// Generate a flop for every entry in the RAM
|
||||||
tlbramline #(`XLEN) tlblineram[NENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
|
tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
|
||||||
|
|
||||||
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
|
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
|
||||||
assign PTEAccessBits = PageTableEntry[7:0];
|
assign PTEAccessBits = PageTableEntry[7:0];
|
||||||
|
Loading…
Reference in New Issue
Block a user