diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 71444cdb..b704aba9 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -138,7 +138,7 @@ add wave /testbench_busybear/InstrMName #add wave -hex /testbench_busybear/dut/hart/dmem/AdrM #add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM #add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCW +add wave -hex /testbench_busybear/PCW ##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW add wave /testbench_busybear/InstrWName #add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index ea63e2ae..5a309b78 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName add wave -divider Write -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcAE #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE @@ -81,7 +81,7 @@ add wave -divider Regfile_signals #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA #add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave -hex /testbench/PCW #add wave /testbench/InstrWName #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 63c2e64f..9318c494 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName add wave -divider Write -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcAE #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE @@ -81,7 +81,7 @@ add wave -divider Regfile_signals #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA #add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave -hex /testbench/PCW #add wave /testbench/InstrWName #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do index a6a0747b..cd2b453b 100644 --- a/wally-pipelined/regression/wave-all.do +++ b/wally-pipelined/regression/wave-all.do @@ -45,7 +45,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA add wave -noupdate -divider -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW +add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate /testbench/InstrWName add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW @@ -219,7 +219,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalCompInstrD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlusUpperF add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlus2or4F add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW +add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkM diff --git a/wally-pipelined/regression/wave-dos/default-waves.do b/wally-pipelined/regression/wave-dos/default-waves.do index 4b645651..76e1c168 100644 --- a/wally-pipelined/regression/wave-dos/default-waves.do +++ b/wally-pipelined/regression/wave-dos/default-waves.do @@ -44,8 +44,8 @@ add wave /testbench/dut/uncore/dtim/memwrite add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 379c7ab4..c3772967 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -125,7 +125,7 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index c68786e5..35844fca 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -192,10 +192,10 @@ module ifu ( flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM); - flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later + // flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later + // flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later flopenrc #(4) InstrClassRegE(.clk(clk), .reset(reset), diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 219869f2..8a75eb81 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -143,6 +143,9 @@ module testbench_busybear(); logic [63:0] pcExpected; logic [63:0] regExpected; integer regNumExpected; + logic [`XLEN-1:0] PCW; + + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); genvar i; generate @@ -349,8 +352,8 @@ module testbench_busybear(); string PCtextW, PCtext2W; logic [31:0] InstrWExpected; logic [63:0] PCWExpected; - always @(dut.hart.ifu.PCW or dut.hart.ieu.InstrValidW) begin - if(dut.hart.ieu.InstrValidW && dut.hart.ifu.PCW != 0) begin + always @(PCW or dut.hart.ieu.InstrValidW) begin + if(dut.hart.ieu.InstrValidW && PCW != 0) begin if($feof(data_file_PCW)) begin $display("no more PC data to read"); `ERROR @@ -363,8 +366,8 @@ module testbench_busybear(); scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected); // then expected PC value scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected); - if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin - $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected); + if(~equal(PCW,PCWExpected,2)) begin + $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, PCW, PCWExpected); `ERROR end //if(it.InstrW != InstrWExpected) begin @@ -481,6 +484,7 @@ module testbench_busybear(); // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, @@ -494,3 +498,128 @@ module testbench_busybear(); end endmodule +module instrTrackerTB( + input logic clk, reset, FlushE, + input logic [31:0] InstrD, + input logic [31:0] InstrE, InstrM, + output logic [31:0] InstrW, + output string InstrDName, InstrEName, InstrMName, InstrWName); + + // stage Instr to Writeback for visualization + //flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + + instrNameDecTB ddec(InstrD, InstrDName); + instrNameDecTB edec(InstrE, InstrEName); + instrNameDecTB mdec(InstrM, InstrMName); + instrNameDecTB wdec(InstrW, InstrWName); +endmodule + +// decode the instruction name, to help the test bench +module instrNameDecTB( + input logic [31:0] instr, + output string name); + + logic [6:0] op; + logic [2:0] funct3; + logic [6:0] funct7; + logic [11:0] imm; + + assign op = instr[6:0]; + assign funct3 = instr[14:12]; + assign funct7 = instr[31:25]; + assign imm = instr[31:20]; + + // it would be nice to add the operands to the name + // create another variable called decoded + + always_comb + casez({op, funct3}) + 10'b0000000_000: name = "BAD"; + 10'b0000011_000: name = "LB"; + 10'b0000011_001: name = "LH"; + 10'b0000011_010: name = "LW"; + 10'b0000011_011: name = "LD"; + 10'b0000011_100: name = "LBU"; + 10'b0000011_101: name = "LHU"; + 10'b0000011_110: name = "LWU"; + 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH"; + else name = "ADDI"; + 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI"; + else name = "ILLEGAL"; + 10'b0010011_010: name = "SLTI"; + 10'b0010011_011: name = "SLTIU"; + 10'b0010011_100: name = "XORI"; + 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI"; + else if (funct7[6:1] == 6'b010000) name = "SRAI"; + else name = "ILLEGAL"; + 10'b0010011_110: name = "ORI"; + 10'b0010011_111: name = "ANDI"; + 10'b0010111_???: name = "AUIPC"; + 10'b0100011_000: name = "SB"; + 10'b0100011_001: name = "SH"; + 10'b0100011_010: name = "SW"; + 10'b0100011_011: name = "SD"; + 10'b0011011_000: name = "ADDIW"; + 10'b0011011_001: name = "SLLIW"; + 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW"; + else if (funct7 == 7'b0100000) name = "SRAIW"; + else name = "ILLEGAL"; + 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; + else if (funct7 == 7'b0100000) name = "SUBW"; + else name = "ILLEGAL"; + 10'b0111011_001: name = "SLLW"; + 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; + else if (funct7 == 7'b0100000) name = "SRAW"; + else name = "ILLEGAL"; + 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; + else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0100000) name = "SUB"; + else name = "ILLEGAL"; + 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; + else if (funct7 == 7'b0000001) name = "MULH"; + else name = "ILLEGAL"; + 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT"; + else if (funct7 == 7'b0000001) name = "MULHSU"; + else name = "ILLEGAL"; + 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; + else if (funct7 == 7'b0000001) name = "DIV"; + else name = "ILLEGAL"; + 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; + else if (funct7 == 7'b0000001) name = "MUL"; + else name = "ILLEGAL"; + 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; + else if (funct7 == 7'b0000001) name = "DIVU"; + else if (funct7 == 7'b0100000) name = "SRA"; + else name = "ILLEGAL"; + 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR"; + else if (funct7 == 7'b0000001) name = "REM"; + else name = "ILLEGAL"; + 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND"; + else if (funct7 == 7'b0000001) name = "REMU"; + else name = "ILLEGAL"; + 10'b0110111_???: name = "LUI"; + 10'b1100011_000: name = "BEQ"; + 10'b1100011_001: name = "BNE"; + 10'b1100011_100: name = "BLT"; + 10'b1100011_101: name = "BGE"; + 10'b1100011_110: name = "BLTU"; + 10'b1100011_111: name = "BGEU"; + 10'b1100111_000: name = "JALR"; + 10'b1101111_???: name = "JAL"; + 10'b1110011_000: if (imm == 0) name = "ECALL"; + else if (imm == 1) name = "EBREAK"; + else if (imm == 2) name = "URET"; + else if (imm == 258) name = "SRET"; + else if (imm == 770) name = "MRET"; + else name = "ILLEGAL"; + 10'b1110011_001: name = "CSRRW"; + 10'b1110011_010: name = "CSRRS"; + 10'b1110011_011: name = "CSRRC"; + 10'b1110011_101: name = "CSRRWI"; + 10'b1110011_110: name = "CSRRSI"; + 10'b1110011_111: name = "CSRRCI"; + 10'b0001111_???: name = "FENCE"; + default: name = "ILLEGAL"; + endcase +endmodule + diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index fbec9f46..eae3ebdc 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -60,12 +60,18 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); // Track names of instructions + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests + + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + integer j; initial begin diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 0035450d..12785539 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -59,12 +59,20 @@ module testbench(); assign HRESPEXT = 0; assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); + + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); + // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + // initialize tests integer j; initial diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 8b128b17..c0b4d0ec 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -38,7 +38,7 @@ module testbench(); logic [`XLEN-1:0] signature[0:10000]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - //logic [31:0] InstrW; + logic [31:0] InstrW; logic [`XLEN-1:0] meminit; string tests64a[] = '{ "rv64a/WALLY-AMO", "2110", @@ -331,8 +331,10 @@ string tests32i[] = { logic [1:0] HTRANS; logic HMASTLOCK; logic HCLK, HRESETn; - + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); // pick tests based on modes supported initial if (`XLEN == 64) begin // RV64 @@ -371,8 +373,8 @@ string tests32i[] = { // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.ic.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, + InstrEName, InstrMName, InstrWName); // initialize tests initial diff --git a/wally-pipelined/testbench/testbench-peripherals.sv b/wally-pipelined/testbench/testbench-peripherals.sv index ba4b94fa..9067fede 100644 --- a/wally-pipelined/testbench/testbench-peripherals.sv +++ b/wally-pipelined/testbench/testbench-peripherals.sv @@ -73,13 +73,15 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); - + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrDName, InstrEName, InstrMName, InstrWName); + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); // initialize tests initial begin @@ -187,7 +189,7 @@ module instrTrackerTB( output string InstrDName, InstrEName, InstrMName, InstrWName); // stage Instr to Writeback for visualization - flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + //flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index f8c519bc..5bcb647c 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -92,13 +92,15 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); - + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); // Track names of instructions instrTrackerTBPriv it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); // initialize tests initial begin @@ -226,7 +228,8 @@ module instrTrackerTBPriv( output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // stage Instr to Writeback for visualization - // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + //flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + instrNameDecTB fdec(InstrF, InstrFName); instrNameDecTB ddec(InstrD, InstrDName);