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Register file comments about reset

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David Harris 2022-02-16 17:21:05 +00:00
parent 03f23d2aaa
commit 799736632b
1 changed files with 1 additions and 0 deletions
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pipelined/src/ieu/regfile.sv
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@ -49,6 +49,7 @@ module regfile (
// register 0 hardwired to 0 // register 0 hardwired to 0
// reset is intended for simulation only, not synthesis // reset is intended for simulation only, not synthesis
// can logic be adjusted to not need resettable registers?
always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset
if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0; if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;