From 799736632b5c24629762d668c97241411def5f6e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 16 Feb 2022 17:21:05 +0000
Subject: [PATCH] Register file comments about reset

---
 pipelined/src/ieu/regfile.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv
index 2dfb0626..71ef621a 100644
--- a/pipelined/src/ieu/regfile.sv
+++ b/pipelined/src/ieu/regfile.sv
@@ -49,6 +49,7 @@ module regfile (
   // register 0 hardwired to 0
   
   // reset is intended for simulation only, not synthesis
+  // can logic be adjusted to not need resettable registers?
     
   always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset
     if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;