forked from Github_Repos/cvw
fpu cleanup
This commit is contained in:
Katherine Parry
commit
6c4aa624a5
@ -2,10 +2,7 @@ onerror {resume}
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quietly WaveActivateNextPane {} 0
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/test
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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@ -14,19 +11,21 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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@ -129,18 +128,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -158,12 +157,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -253,61 +252,61 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
@ -316,17 +315,16 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
@ -352,12 +350,21 @@ add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu
|
|||||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/hptw/genblk1/PRegEn
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {7778 ns} 0}
|
WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {2898 ns} 0}
|
||||||
quietly wave cursor active 4
|
quietly wave cursor active 4
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
@ -373,4 +380,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {7636 ns} {7946 ns}
|
WaveRestoreZoom {2835 ns} {2995 ns}
|
||||||
|
|||||||
16
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
16
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
@ -115,7 +115,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
|
localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
|
||||||
localparam STATE_TLB_MISS = 'h13;
|
localparam STATE_TLB_MISS = 'h13;
|
||||||
localparam STATE_TLB_MISS_DONE = 'h14;
|
localparam STATE_TLB_MISS_DONE = 'h14;
|
||||||
localparam STATE_INSTR_PAGE_FAULT = 'h15;
|
|
||||||
|
|
||||||
|
|
||||||
localparam AHBByteLength = `XLEN / 8;
|
localparam AHBByteLength = `XLEN / 8;
|
||||||
@ -141,7 +140,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
logic FetchCountFlag;
|
logic FetchCountFlag;
|
||||||
localparam FetchCountThreshold = WORDSPERLINE - 1;
|
localparam FetchCountThreshold = WORDSPERLINE - 1;
|
||||||
|
|
||||||
logic [LOGWPL:0] FetchCount, NextFetchCount;
|
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
||||||
|
|
||||||
logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
|
logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
|
||||||
logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
|
logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
|
||||||
@ -195,10 +194,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
|
|
||||||
assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
|
assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
|
||||||
assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
|
assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
|
||||||
// verilator lint_off WIDTH
|
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
||||||
// *** Bug width is wrong.
|
|
||||||
assign FetchCountFlag = (FetchCount == FetchCountThreshold);
|
|
||||||
// verilator lint_on WIDTH
|
|
||||||
|
|
||||||
// Next state logic
|
// Next state logic
|
||||||
always_comb begin
|
always_comb begin
|
||||||
@ -372,7 +368,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
end
|
end
|
||||||
STATE_TLB_MISS: begin
|
STATE_TLB_MISS: begin
|
||||||
if (WalkerInstrPageFaultF) begin
|
if (WalkerInstrPageFaultF) begin
|
||||||
NextState = STATE_INSTR_PAGE_FAULT;
|
NextState = STATE_READY;
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
end else if (ITLBWriteF) begin
|
end else if (ITLBWriteF) begin
|
||||||
NextState = STATE_TLB_MISS_DONE;
|
NextState = STATE_TLB_MISS_DONE;
|
||||||
@ -383,10 +379,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
STATE_TLB_MISS_DONE: begin
|
STATE_TLB_MISS_DONE: begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
STATE_INSTR_PAGE_FAULT: begin
|
|
||||||
ICacheStallF = 1'b0;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
default: begin
|
default: begin
|
||||||
PCMux = 2'b01;
|
PCMux = 2'b01;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -404,7 +396,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
|
|||||||
// to compute the fetch address we need to add the bit shifted
|
// to compute the fetch address we need to add the bit shifted
|
||||||
// counter output to the address.
|
// counter output to the address.
|
||||||
|
|
||||||
flopenr #(LOGWPL+1)
|
flopenr #(LOGWPL)
|
||||||
FetchCountReg(.clk(clk),
|
FetchCountReg(.clk(clk),
|
||||||
.reset(reset | CntReset),
|
.reset(reset | CntReset),
|
||||||
.en(CntEn),
|
.en(CntEn),
|
||||||
|
|||||||
84
wally-pipelined/src/cache/dcache.sv
vendored
84
wally-pipelined/src/cache/dcache.sv
vendored
@ -29,7 +29,7 @@ module dcache
|
|||||||
(input logic clk,
|
(input logic clk,
|
||||||
input logic reset,
|
input logic reset,
|
||||||
input logic StallM,
|
input logic StallM,
|
||||||
input logic StallW,
|
input logic StallWtoDCache,
|
||||||
input logic FlushM,
|
input logic FlushM,
|
||||||
input logic FlushW,
|
input logic FlushW,
|
||||||
|
|
||||||
@ -43,7 +43,6 @@ module dcache
|
|||||||
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
||||||
|
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
|
||||||
output logic [`XLEN-1:0] ReadDataM,
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
output logic DCacheStall,
|
output logic DCacheStall,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
@ -57,9 +56,11 @@ module dcache
|
|||||||
input logic CacheableM,
|
input logic CacheableM,
|
||||||
input logic DTLBWriteM,
|
input logic DTLBWriteM,
|
||||||
input logic ITLBWriteF,
|
input logic ITLBWriteF,
|
||||||
|
input logic WalkerInstrPageFaultF,
|
||||||
// from ptw
|
// from ptw
|
||||||
input logic SelPTW,
|
input logic SelPTW,
|
||||||
input logic WalkerPageFaultM,
|
input logic WalkerPageFaultM,
|
||||||
|
output logic [`XLEN-1:0] LSUData,
|
||||||
// ahb side
|
// ahb side
|
||||||
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
||||||
output logic AHBRead,
|
output logic AHBRead,
|
||||||
@ -108,7 +109,7 @@ module dcache
|
|||||||
logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
|
logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
|
||||||
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
|
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
|
||||||
logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
|
logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
|
||||||
logic [LOGWPL:0] FetchCount, NextFetchCount;
|
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
||||||
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
||||||
logic SelMemWriteDataM;
|
logic SelMemWriteDataM;
|
||||||
logic [2:0] Funct3W;
|
logic [2:0] Funct3W;
|
||||||
@ -148,6 +149,11 @@ module dcache
|
|||||||
|
|
||||||
logic LRUWriteEn;
|
logic LRUWriteEn;
|
||||||
|
|
||||||
|
logic CaptureDataM;
|
||||||
|
logic [`XLEN-1:0] SavedReadDataM;
|
||||||
|
logic SelSavedReadDataM;
|
||||||
|
|
||||||
|
|
||||||
typedef enum {STATE_READY,
|
typedef enum {STATE_READY,
|
||||||
|
|
||||||
STATE_MISS_FETCH_WDV,
|
STATE_MISS_FETCH_WDV,
|
||||||
@ -193,7 +199,7 @@ module dcache
|
|||||||
|
|
||||||
flopenr #(7) Funct7WReg(.clk(clk),
|
flopenr #(7) Funct7WReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.en(~StallW),
|
.en(~StallWtoDCache),
|
||||||
.d(Funct7M),
|
.d(Funct7M),
|
||||||
.q(Funct7W));
|
.q(Funct7W));
|
||||||
|
|
||||||
@ -319,10 +325,7 @@ module dcache
|
|||||||
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
|
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
|
||||||
|
|
||||||
|
|
||||||
// *** fix width later.
|
|
||||||
// verilator lint_off WIDTH
|
|
||||||
assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
|
assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
|
||||||
// verilator lint_on WIDTH
|
|
||||||
|
|
||||||
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
|
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
|
||||||
.d1(DCacheMemWriteData[`XLEN-1:0]),
|
.d1(DCacheMemWriteData[`XLEN-1:0]),
|
||||||
@ -334,10 +337,27 @@ module dcache
|
|||||||
subwordread subwordread(.HRDATA(ReadDataWordMuxM),
|
subwordread subwordread(.HRDATA(ReadDataWordMuxM),
|
||||||
.HADDRD(MemPAdrM[2:0]),
|
.HADDRD(MemPAdrM[2:0]),
|
||||||
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
|
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
|
||||||
.HRDATAMasked(ReadDataM));
|
.HRDATAMasked(LSUData));
|
||||||
|
|
||||||
|
assign CaptureDataM = ~SelPTW & MemRWM[1];
|
||||||
|
|
||||||
|
flopen #(`XLEN)
|
||||||
|
SavedReadDataReg(.clk,
|
||||||
|
.en(CaptureDataM),
|
||||||
|
.d(LSUData),
|
||||||
|
.q(SavedReadDataM));
|
||||||
|
|
||||||
|
|
||||||
|
mux2 #(`XLEN)
|
||||||
|
ReadDataMMux(.d0(LSUData),
|
||||||
|
.d1(SavedReadDataM),
|
||||||
|
.s(SelSavedReadDataM),
|
||||||
|
.y(ReadDataM));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// This is a confusing point.
|
// This is a confusing point.
|
||||||
// The final read data should be updated only if the CPU's StallW is low
|
// The final read data should be updated only if the CPU's StallWtoDCache is low
|
||||||
// which means the CPU is ready to take data. Or if the CPU just became
|
// which means the CPU is ready to take data. Or if the CPU just became
|
||||||
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
||||||
// updated, this is ~PreviousCPUBusy.
|
// updated, this is ~PreviousCPUBusy.
|
||||||
@ -347,10 +367,6 @@ module dcache
|
|||||||
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
||||||
|
|
||||||
|
|
||||||
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
|
||||||
.en(~StallW),
|
|
||||||
.d(ReadDataM),
|
|
||||||
.q(ReadDataW));
|
|
||||||
|
|
||||||
|
|
||||||
// write path
|
// write path
|
||||||
@ -381,24 +397,18 @@ module dcache
|
|||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
// *** Coding style. this is just awful. The purpose is to align FetchCount to the
|
|
||||||
// size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length.
|
|
||||||
// *** optimize this
|
|
||||||
mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
||||||
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||||
.s(SelEvict),
|
.s(SelEvict),
|
||||||
.y(BasePAdrM));
|
.y(BasePAdrM));
|
||||||
|
|
||||||
|
// if not cacheable the offset bits needs to be sent to the EBU.
|
||||||
|
// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
|
||||||
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
||||||
assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
|
assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
|
||||||
|
|
||||||
generate
|
assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
|
||||||
if (`XLEN == 32) begin
|
|
||||||
assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM;
|
|
||||||
end else begin
|
|
||||||
assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM;
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
|
|
||||||
// mux between the CPU's write and the cache fetch.
|
// mux between the CPU's write and the cache fetch.
|
||||||
@ -422,9 +432,9 @@ module dcache
|
|||||||
|
|
||||||
|
|
||||||
assign AnyCPUReqM = |MemRWM | (|AtomicM);
|
assign AnyCPUReqM = |MemRWM | (|AtomicM);
|
||||||
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
|
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
||||||
|
|
||||||
flopenr #(LOGWPL+1)
|
flopenr #(LOGWPL)
|
||||||
FetchCountReg(.clk(clk),
|
FetchCountReg(.clk(clk),
|
||||||
.reset(reset | CntReset),
|
.reset(reset | CntReset),
|
||||||
.en(CntEn),
|
.en(CntEn),
|
||||||
@ -470,6 +480,7 @@ module dcache
|
|||||||
DCacheAccess = 1'b0;
|
DCacheAccess = 1'b0;
|
||||||
DCacheMiss = 1'b0;
|
DCacheMiss = 1'b0;
|
||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
|
SelSavedReadDataM = 1'b0;
|
||||||
|
|
||||||
case (CurrState)
|
case (CurrState)
|
||||||
STATE_READY: begin
|
STATE_READY: begin
|
||||||
@ -496,7 +507,7 @@ module dcache
|
|||||||
NextState = STATE_AMO_UPDATE;
|
NextState = STATE_AMO_UPDATE;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
else NextState = STATE_AMO_UPDATE;
|
else NextState = STATE_AMO_UPDATE;
|
||||||
@ -508,7 +519,7 @@ module dcache
|
|||||||
DCacheAccess = 1'b1;
|
DCacheAccess = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -523,7 +534,7 @@ module dcache
|
|||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -565,7 +576,7 @@ module dcache
|
|||||||
end
|
end
|
||||||
STATE_AMO_WRITE: begin
|
STATE_AMO_WRITE: begin
|
||||||
SelAMOWrite = 1'b1;
|
SelAMOWrite = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -626,7 +637,7 @@ module dcache
|
|||||||
//SelAdrM = 1'b1;
|
//SelAdrM = 1'b1;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -645,7 +656,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_MISS_WRITE_WORD_DELAY: begin
|
STATE_MISS_WRITE_WORD_DELAY: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -670,8 +681,11 @@ module dcache
|
|||||||
// now all output connect to PTW instead of CPU.
|
// now all output connect to PTW instead of CPU.
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
|
|
||||||
if (ITLBWriteF) begin
|
if (ITLBWriteF | WalkerInstrPageFaultF) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
// this signal is gross. It is used to select the saved read data m when the
|
||||||
|
// CPU was stalled for an itlb miss with a simultaneous load.
|
||||||
|
SelSavedReadDataM = 1'b1;
|
||||||
end
|
end
|
||||||
|
|
||||||
// return to ready if page table walk completed.
|
// return to ready if page table walk completed.
|
||||||
@ -782,7 +796,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -813,7 +827,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_UNCACHED_WRITE_DONE: begin
|
STATE_UNCACHED_WRITE_DONE: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -823,7 +837,7 @@ module dcache
|
|||||||
STATE_UNCACHED_READ_DONE: begin
|
STATE_UNCACHED_READ_DONE: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
SelUncached = 1'b1;
|
SelUncached = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -40,10 +40,6 @@ module unpacking (
|
|||||||
assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23];
|
assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23];
|
||||||
assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23];
|
assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23];
|
||||||
|
|
||||||
assign XManE = {XExpNonzero, XFracE};
|
|
||||||
assign YManE = {YExpNonzero, YFracE};
|
|
||||||
assign ZManE = {ZExpNonzero, ZFracE};
|
|
||||||
|
|
||||||
assign XExpZero = ~XExpNonzero;
|
assign XExpZero = ~XExpNonzero;
|
||||||
assign YExpZero = ~YExpNonzero;
|
assign YExpZero = ~YExpNonzero;
|
||||||
assign ZExpZero = ~ZExpNonzero;
|
assign ZExpZero = ~ZExpNonzero;
|
||||||
@ -52,6 +48,10 @@ module unpacking (
|
|||||||
assign YFracZero = ~|YFracE;
|
assign YFracZero = ~|YFracE;
|
||||||
assign ZFracZero = ~|ZFracE;
|
assign ZFracZero = ~|ZFracE;
|
||||||
|
|
||||||
|
assign XManE = {XExpNonzero, XFracE};
|
||||||
|
assign YManE = {YExpNonzero, YFracE};
|
||||||
|
assign ZManE = {ZExpNonzero, ZFracE};
|
||||||
|
|
||||||
assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23];
|
assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23];
|
||||||
assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23];
|
assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23];
|
||||||
assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23];
|
assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23];
|
||||||
|
|||||||
@ -57,8 +57,9 @@ module datapath (
|
|||||||
input logic RegWriteW,
|
input logic RegWriteW,
|
||||||
input logic SquashSCW,
|
input logic SquashSCW,
|
||||||
input logic [2:0] ResultSrcW,
|
input logic [2:0] ResultSrcW,
|
||||||
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
// input logic [`XLEN-1:0] PCLinkW,
|
// input logic [`XLEN-1:0] PCLinkW,
|
||||||
input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW,
|
input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
|
||||||
// Hazard Unit signals
|
// Hazard Unit signals
|
||||||
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
|
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
|
||||||
output logic [4:0] RdE, RdM, RdW
|
output logic [4:0] RdE, RdM, RdW
|
||||||
@ -137,6 +138,11 @@ module datapath (
|
|||||||
assign SCResultW = 0;
|
assign SCResultW = 0;
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
||||||
|
.en(~StallW),
|
||||||
|
.d(ReadDataM),
|
||||||
|
.q(ReadDataW));
|
||||||
|
|
||||||
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
|
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
// This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage.
|
// This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage.
|
||||||
|
|||||||
@ -61,9 +61,10 @@ module ieu (
|
|||||||
input logic [`XLEN-1:0] FIntResM,
|
input logic [`XLEN-1:0] FIntResM,
|
||||||
|
|
||||||
// Writeback stage
|
// Writeback stage
|
||||||
input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW,
|
input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
|
||||||
input logic FWriteIntW,
|
input logic FWriteIntW,
|
||||||
output logic [4:0] RdW,
|
output logic [4:0] RdW,
|
||||||
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
// input logic [`XLEN-1:0] PCLinkW,
|
// input logic [`XLEN-1:0] PCLinkW,
|
||||||
output logic InstrValidM,
|
output logic InstrValidM,
|
||||||
// hazards
|
// hazards
|
||||||
|
|||||||
@ -52,7 +52,7 @@ module lsu
|
|||||||
input logic [`XLEN-1:0] MemAdrM,
|
input logic [`XLEN-1:0] MemAdrM,
|
||||||
input logic [`XLEN-1:0] MemAdrE,
|
input logic [`XLEN-1:0] MemAdrE,
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
|
|
||||||
// cpu privilege
|
// cpu privilege
|
||||||
input logic [1:0] PrivilegeModeW,
|
input logic [1:0] PrivilegeModeW,
|
||||||
@ -121,7 +121,6 @@ module lsu
|
|||||||
logic DTLBMissM;
|
logic DTLBMissM;
|
||||||
// logic [`XLEN-1:0] PTE;
|
// logic [`XLEN-1:0] PTE;
|
||||||
logic DTLBWriteM;
|
logic DTLBWriteM;
|
||||||
logic [`XLEN-1:0] HPTWReadPTE;
|
|
||||||
logic HPTWStall;
|
logic HPTWStall;
|
||||||
logic [`XLEN-1:0] HPTWPAdrE;
|
logic [`XLEN-1:0] HPTWPAdrE;
|
||||||
// logic [`XLEN-1:0] HPTWPAdrM;
|
// logic [`XLEN-1:0] HPTWPAdrM;
|
||||||
@ -150,6 +149,7 @@ module lsu
|
|||||||
logic FlushWtoDCache;
|
logic FlushWtoDCache;
|
||||||
logic WalkerPageFaultM;
|
logic WalkerPageFaultM;
|
||||||
|
|
||||||
|
logic [`XLEN-1:0] LSUData;
|
||||||
|
|
||||||
hptw hptw(
|
hptw hptw(
|
||||||
.clk(clk),
|
.clk(clk),
|
||||||
@ -164,7 +164,7 @@ module lsu
|
|||||||
.PageType,
|
.PageType,
|
||||||
.ITLBWriteF(ITLBWriteF),
|
.ITLBWriteF(ITLBWriteF),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
.DTLBWriteM(DTLBWriteM),
|
||||||
.HPTWReadPTE(HPTWReadPTE),
|
.HPTWReadPTE(LSUData),
|
||||||
.HPTWStall(HPTWStall),
|
.HPTWStall(HPTWStall),
|
||||||
.TranslationPAdr,
|
.TranslationPAdr,
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWRead(HPTWRead),
|
||||||
@ -193,7 +193,6 @@ module lsu
|
|||||||
.CommittedM(CommittedM),
|
.CommittedM(CommittedM),
|
||||||
.PendingInterruptM(PendingInterruptM),
|
.PendingInterruptM(PendingInterruptM),
|
||||||
.StallW(StallW),
|
.StallW(StallW),
|
||||||
.ReadDataW(ReadDataW),
|
|
||||||
.DataMisalignedM(DataMisalignedM),
|
.DataMisalignedM(DataMisalignedM),
|
||||||
.LSUStall(LSUStall),
|
.LSUStall(LSUStall),
|
||||||
// DCACHE
|
// DCACHE
|
||||||
@ -205,7 +204,6 @@ module lsu
|
|||||||
.MemAdrEtoDCache(MemAdrEtoDCache),
|
.MemAdrEtoDCache(MemAdrEtoDCache),
|
||||||
.StallWtoDCache(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||||
.ReadDataWfromDCache(ReadDataWfromDCache),
|
|
||||||
.CommittedMfromDCache(CommittedMfromDCache),
|
.CommittedMfromDCache(CommittedMfromDCache),
|
||||||
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
||||||
.DCacheStall(DCacheStall));
|
.DCacheStall(DCacheStall));
|
||||||
@ -294,7 +292,7 @@ module lsu
|
|||||||
dcache dcache(.clk(clk),
|
dcache dcache(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.StallM(StallM),
|
.StallM(StallM),
|
||||||
.StallW(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.FlushM(FlushM),
|
.FlushM(FlushM),
|
||||||
.FlushW(FlushWtoDCache),
|
.FlushW(FlushWtoDCache),
|
||||||
.MemRWM(MemRWMtoDCache),
|
.MemRWM(MemRWMtoDCache),
|
||||||
@ -305,8 +303,8 @@ module lsu
|
|||||||
.MemPAdrM(MemPAdrM),
|
.MemPAdrM(MemPAdrM),
|
||||||
.VAdr(MemAdrM[11:0]),
|
.VAdr(MemAdrM[11:0]),
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataWfromDCache),
|
.ReadDataM(ReadDataM),
|
||||||
.ReadDataM(HPTWReadPTE),
|
.LSUData(LSUData),
|
||||||
.DCacheStall(DCacheStall),
|
.DCacheStall(DCacheStall),
|
||||||
.CommittedM(CommittedMfromDCache),
|
.CommittedM(CommittedMfromDCache),
|
||||||
.DCacheMiss,
|
.DCacheMiss,
|
||||||
@ -319,6 +317,7 @@ module lsu
|
|||||||
.ITLBWriteF(ITLBWriteF),
|
.ITLBWriteF(ITLBWriteF),
|
||||||
.SelPTW(SelPTW),
|
.SelPTW(SelPTW),
|
||||||
.WalkerPageFaultM(WalkerPageFaultM),
|
.WalkerPageFaultM(WalkerPageFaultM),
|
||||||
|
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||||
|
|
||||||
// AHB connection
|
// AHB connection
|
||||||
.AHBPAdr(DCtoAHBPAdrM),
|
.AHBPAdr(DCtoAHBPAdrM),
|
||||||
|
|||||||
@ -44,7 +44,6 @@ module lsuArb
|
|||||||
input logic StallW,
|
input logic StallW,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
// to CPU
|
// to CPU
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
|
||||||
output logic DataMisalignedM,
|
output logic DataMisalignedM,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
output logic LSUStall,
|
output logic LSUStall,
|
||||||
@ -63,7 +62,6 @@ module lsuArb
|
|||||||
// from D Cache
|
// from D Cache
|
||||||
input logic CommittedMfromDCache,
|
input logic CommittedMfromDCache,
|
||||||
input logic DataMisalignedMfromDCache,
|
input logic DataMisalignedMfromDCache,
|
||||||
input logic [`XLEN-1:0] ReadDataWfromDCache,
|
|
||||||
input logic DCacheStall
|
input logic DCacheStall
|
||||||
|
|
||||||
);
|
);
|
||||||
@ -95,7 +93,6 @@ module lsuArb
|
|||||||
// demux the inputs from LSU to walker or cpu's data port.
|
// demux the inputs from LSU to walker or cpu's data port.
|
||||||
|
|
||||||
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
|
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
|
||||||
assign ReadDataW = /*SelPTW ? `XLEN'b0 : */ReadDataWfromDCache; // probably can avoid this demux
|
|
||||||
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
|
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
|
||||||
// *** need to rename DcacheStall and Datastall.
|
// *** need to rename DcacheStall and Datastall.
|
||||||
// not clear at all. I think it should be LSUStall from the LSU,
|
// not clear at all. I think it should be LSUStall from the LSU,
|
||||||
|
|||||||
@ -48,6 +48,12 @@ module hptw
|
|||||||
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
|
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
|
||||||
);
|
);
|
||||||
|
|
||||||
|
typedef enum {L0_ADR, L0_RD,
|
||||||
|
L1_ADR, L1_RD,
|
||||||
|
L2_ADR, L2_RD,
|
||||||
|
L3_ADR, L3_RD,
|
||||||
|
LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`MEM_VIRTMEM) begin
|
if (`MEM_VIRTMEM) begin
|
||||||
logic DTLBWalk; // register TLBs translation miss requests
|
logic DTLBWalk; // register TLBs translation miss requests
|
||||||
@ -64,12 +70,6 @@ module hptw
|
|||||||
logic [`SVMODE_BITS-1:0] SvMode;
|
logic [`SVMODE_BITS-1:0] SvMode;
|
||||||
logic [`XLEN-1:0] TranslationVAdr;
|
logic [`XLEN-1:0] TranslationVAdr;
|
||||||
|
|
||||||
|
|
||||||
typedef enum {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0,
|
|
||||||
LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1,
|
|
||||||
LEVEL2_SET_ADR, LEVEL2_READ, LEVEL2,
|
|
||||||
LEVEL3_SET_ADR, LEVEL3_READ, LEVEL3,
|
|
||||||
LEAF, IDLE, FAULT} statetype;
|
|
||||||
statetype WalkerState, NextWalkerState, InitialWalkerState;
|
statetype WalkerState, NextWalkerState, InitialWalkerState;
|
||||||
|
|
||||||
// Extract bits from CSRs and inputs
|
// Extract bits from CSRs and inputs
|
||||||
@ -97,7 +97,7 @@ module hptw
|
|||||||
|
|
||||||
// Enable and select signals based on states
|
// Enable and select signals based on states
|
||||||
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
||||||
assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ);
|
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
|
||||||
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
|
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
|
||||||
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
||||||
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
||||||
@ -111,10 +111,10 @@ module hptw
|
|||||||
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
||||||
always_comb
|
always_comb
|
||||||
case (WalkerState)
|
case (WalkerState)
|
||||||
LEVEL3: NextPageType = 2'b11; // terapage
|
L3_RD: NextPageType = 2'b11; // terapage
|
||||||
LEVEL2: NextPageType = 2'b10; // gigapage
|
L2_RD: NextPageType = 2'b10; // gigapage
|
||||||
LEVEL1: NextPageType = 2'b01; // megapage
|
L1_RD: NextPageType = 2'b01; // megapage
|
||||||
LEVEL0: NextPageType = 2'b00; // kilopage
|
L0_RD: NextPageType = 2'b00; // kilopage
|
||||||
default: NextPageType = PageType;
|
default: NextPageType = PageType;
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
@ -122,36 +122,36 @@ module hptw
|
|||||||
if (`XLEN==32) begin // RV32
|
if (`XLEN==32) begin // RV32
|
||||||
logic [9:0] VPN;
|
logic [9:0] VPN;
|
||||||
logic [`PPN_BITS-1:0] PPN;
|
logic [`PPN_BITS-1:0] PPN;
|
||||||
assign VPN = ((WalkerState == LEVEL1_SET_ADR) | (WalkerState == LEVEL1_READ)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
|
assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
|
||||||
assign PPN = ((WalkerState == LEVEL1_SET_ADR) | (WalkerState == LEVEL1_READ)) ? BasePageTablePPN : CurrentPPN;
|
assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
|
||||||
assign TranslationPAdr = {PPN, VPN, 2'b00};
|
assign TranslationPAdr = {PPN, VPN, 2'b00};
|
||||||
end else begin // RV64
|
end else begin // RV64
|
||||||
logic [8:0] VPN;
|
logic [8:0] VPN;
|
||||||
logic [`PPN_BITS-1:0] PPN;
|
logic [`PPN_BITS-1:0] PPN;
|
||||||
always_comb
|
always_comb
|
||||||
case (WalkerState) // select VPN field based on HPTW state
|
case (WalkerState) // select VPN field based on HPTW state
|
||||||
LEVEL3_SET_ADR, LEVEL3_READ: VPN = TranslationVAdr[47:39];
|
L3_ADR, L3_RD: VPN = TranslationVAdr[47:39];
|
||||||
LEVEL3, LEVEL2_SET_ADR, LEVEL2_READ: VPN = TranslationVAdr[38:30];
|
L2_ADR, L2_RD: VPN = TranslationVAdr[38:30];
|
||||||
LEVEL2, LEVEL1_SET_ADR, LEVEL1_READ: VPN = TranslationVAdr[29:21];
|
L1_ADR, L1_RD: VPN = TranslationVAdr[29:21];
|
||||||
default: VPN = TranslationVAdr[20:12];
|
default: VPN = TranslationVAdr[20:12];
|
||||||
endcase
|
endcase
|
||||||
assign PPN = ((WalkerState == LEVEL3_SET_ADR) | (WalkerState == LEVEL3_READ) |
|
assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
|
||||||
(SvMode != `SV48 & ((WalkerState == LEVEL2_SET_ADR) | (WalkerState == LEVEL2_READ)))) ? BasePageTablePPN : CurrentPPN;
|
(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
|
||||||
assign TranslationPAdr = {PPN, VPN, 3'b000};
|
assign TranslationPAdr = {PPN, VPN, 3'b000};
|
||||||
end
|
end
|
||||||
|
|
||||||
// Initial state and misalignment for RV32/64
|
// Initial state and misalignment for RV32/64
|
||||||
if (`XLEN == 32) begin
|
if (`XLEN == 32) begin
|
||||||
assign InitialWalkerState = LEVEL1_SET_ADR;
|
assign InitialWalkerState = L1_ADR;
|
||||||
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
|
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
|
||||||
assign Misaligned = ((WalkerState == LEVEL1) & MegapageMisaligned);
|
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||||
end else begin
|
end else begin
|
||||||
logic GigapageMisaligned, TerapageMisaligned;
|
logic GigapageMisaligned, TerapageMisaligned;
|
||||||
assign InitialWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADR : LEVEL2_SET_ADR;
|
assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
|
||||||
assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
|
assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
|
||||||
assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
|
assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
|
||||||
assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
|
assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
|
||||||
assign Misaligned = ((WalkerState == LEVEL3) & TerapageMisaligned) | ((WalkerState == LEVEL2) & GigapageMisaligned) | ((WalkerState == LEVEL1) & MegapageMisaligned);
|
assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||||
end
|
end
|
||||||
|
|
||||||
// Page Table Walker FSM
|
// Page Table Walker FSM
|
||||||
@ -164,29 +164,37 @@ module hptw
|
|||||||
case (WalkerState)
|
case (WalkerState)
|
||||||
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
||||||
else NextWalkerState = IDLE;
|
else NextWalkerState = IDLE;
|
||||||
LEVEL3_SET_ADR: NextWalkerState = LEVEL3_READ;
|
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
|
||||||
LEVEL3_READ: if (HPTWStall) NextWalkerState = LEVEL3_READ;
|
L3_RD: if (HPTWStall) NextWalkerState = L3_RD;
|
||||||
else NextWalkerState = LEVEL3;
|
else NextWalkerState = L2_ADR;
|
||||||
LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = LEVEL2_SET_ADR;
|
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
|
||||||
|
// else NextWalkerState = FAULT;
|
||||||
|
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
||||||
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
|
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
LEVEL2_SET_ADR: NextWalkerState = LEVEL2_READ;
|
L2_RD: if (HPTWStall) NextWalkerState = L2_RD;
|
||||||
LEVEL2_READ: if (HPTWStall) NextWalkerState = LEVEL2_READ;
|
else NextWalkerState = L1_ADR;
|
||||||
else NextWalkerState = LEVEL2;
|
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = LEVEL1_SET_ADR;
|
// else NextWalkerState = FAULT;
|
||||||
|
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
||||||
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
|
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
LEVEL1_SET_ADR: NextWalkerState = LEVEL1_READ;
|
L1_RD: if (HPTWStall) NextWalkerState = L1_RD;
|
||||||
LEVEL1_READ: if (HPTWStall) NextWalkerState = LEVEL1_READ;
|
else NextWalkerState = L0_ADR;
|
||||||
else NextWalkerState = LEVEL1;
|
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = LEVEL0_SET_ADR;
|
// else NextWalkerState = FAULT;
|
||||||
else NextWalkerState = FAULT;
|
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
LEVEL0_SET_ADR: NextWalkerState = LEVEL0_READ;
|
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||||
LEVEL0_READ: if (HPTWStall) NextWalkerState = LEVEL0_READ;
|
|
||||||
else NextWalkerState = LEVEL0;
|
|
||||||
LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
|
L0_RD: if (HPTWStall) NextWalkerState = L0_RD;
|
||||||
|
else NextWalkerState = LEAF;
|
||||||
|
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||||
|
// else NextWalkerState = FAULT;
|
||||||
LEAF: NextWalkerState = IDLE;
|
LEAF: NextWalkerState = IDLE;
|
||||||
FAULT: NextWalkerState = IDLE;
|
FAULT: NextWalkerState = IDLE;
|
||||||
default: begin
|
default: begin
|
||||||
|
|||||||
@ -67,9 +67,7 @@ module pmpadrdec (
|
|||||||
assign TORMatch = PAgePMPAdrIn && PAltPMPAdr;
|
assign TORMatch = PAgePMPAdrIn && PAltPMPAdr;
|
||||||
|
|
||||||
// Naturally aligned regions
|
// Naturally aligned regions
|
||||||
|
logic [`PA_BITS-1:0] NAMask;
|
||||||
// verilator lint_off UNOPTFLAT
|
|
||||||
logic [`PA_BITS-1:0] Mask;
|
|
||||||
//genvar i;
|
//genvar i;
|
||||||
|
|
||||||
// create a mask of which bits to ignore
|
// create a mask of which bits to ignore
|
||||||
@ -80,23 +78,14 @@ module pmpadrdec (
|
|||||||
// assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
|
// assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
|
||||||
// end
|
// end
|
||||||
// endgenerate
|
// endgenerate
|
||||||
prioritycircuit #(.ENTRIES(`PA_BITS-2), .FINAL_OP("NONE")) maskgen(.a(~PMPAdr[`PA_BITS-3:0]), .FirstPin(AdrMode==NAPOT), .y(Mask[`PA_BITS-1:2]));
|
|
||||||
assign Mask[1:0] = 2'b11;
|
|
||||||
|
|
||||||
// *** possible experiments:
|
assign NAMask[1:0] = {2'b11};
|
||||||
/* PA < PMP addr could be in its own module,
|
|
||||||
preeserving hierarchy so we can know if this is the culprit on the critical path
|
|
||||||
Should take logarthmic time, so more like 6 levels than 40 should be expected
|
|
||||||
|
|
||||||
update mask generation
|
prioritythemometer #(`PA_BITS-2) namaskgen(
|
||||||
Should be concurrent with the subtraction/comparison
|
.a({PMPAdr[`PA_BITS-4:0], (AdrMode == NAPOT)}),
|
||||||
if one is the critical path, the other shouldn't be which makes us think the mask generation is the culprit.
|
.y(NAMask[`PA_BITS-1:2]));
|
||||||
|
|
||||||
Hopefully just use the priority circuit here
|
assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | NAMask);
|
||||||
*/
|
|
||||||
// verilator lint_on UNOPTFLAT
|
|
||||||
|
|
||||||
assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask);
|
|
||||||
|
|
||||||
assign Match = (AdrMode == TOR) ? TORMatch :
|
assign Match = (AdrMode == TOR) ? TORMatch :
|
||||||
(AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
|
(AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
|
||||||
|
|||||||
@ -69,7 +69,7 @@ module pmpchecker (
|
|||||||
.PAgePMPAdrOut(PAgePMPAdr),
|
.PAgePMPAdrOut(PAgePMPAdr),
|
||||||
.FirstMatch, .Match, .Active, .L, .X, .W, .R);
|
.FirstMatch, .Match, .Active, .L, .X, .W, .R);
|
||||||
|
|
||||||
prioritycircuit #(.ENTRIES(`PMP_ENTRIES), .FINAL_OP("AND")) pmppriority(.a(Match), .FirstPin(1'b1), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit.
|
priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit.
|
||||||
|
|
||||||
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
||||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
|
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
// prioritycircuit.sv
|
// priorityonehot.sv
|
||||||
//
|
//
|
||||||
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
|
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
|
||||||
// Modified: Teo Ene 15 Apr 2021:
|
// Modified: Teo Ene 15 Apr 2021:
|
||||||
@ -30,31 +30,22 @@
|
|||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module prioritycircuit #(parameter ENTRIES = 8,
|
module priorityonehot #(parameter ENTRIES = 8) (
|
||||||
parameter FINAL_OP = "AND") (
|
|
||||||
input logic [ENTRIES-1:0] a,
|
input logic [ENTRIES-1:0] a,
|
||||||
input logic FirstPin,
|
|
||||||
output logic [ENTRIES-1:0] y
|
output logic [ENTRIES-1:0] y
|
||||||
);
|
);
|
||||||
// verilator lint_off UNOPTFLAT
|
|
||||||
logic [ENTRIES-1:0] nolower;
|
logic [ENTRIES-1:0] nolower;
|
||||||
|
|
||||||
// generate thermometer code mask
|
// generate thermometer code mask
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
generate
|
||||||
assign nolower[0] = FirstPin;
|
assign nolower[0] = 1'b1;
|
||||||
for (i=1; i<ENTRIES; i++) begin:therm
|
for (i=1; i<ENTRIES; i++) begin:therm
|
||||||
assign nolower[i] = nolower[i-1] & ~a[i-1];
|
assign nolower[i] = nolower[i-1] & ~a[i-1];
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
// verilator lint_on UNOPTFLAT
|
|
||||||
|
|
||||||
generate
|
|
||||||
if (FINAL_OP=="AND") begin
|
|
||||||
assign y = a & nolower;
|
assign y = a & nolower;
|
||||||
end else if (FINAL_OP=="NONE") begin
|
|
||||||
assign y = nolower;
|
|
||||||
end // *** So far these are the only two operations I need to do at the end, but feel free to add more as needed.
|
|
||||||
endgenerate
|
|
||||||
// assign y = a & nolower;
|
|
||||||
endmodule
|
endmodule
|
||||||
50
wally-pipelined/src/mmu/prioritythermometer.sv
Normal file
50
wally-pipelined/src/mmu/prioritythermometer.sv
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
// priritythermometer.sv
|
||||||
|
//
|
||||||
|
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
|
||||||
|
// Modified: Teo Ene 15 Apr 2021:
|
||||||
|
// Temporarily removed paramterized priority encoder for non-parameterized one
|
||||||
|
// To get synthesis working quickly
|
||||||
|
// Kmacsaigoren@hmc.edu 28 May 2021:
|
||||||
|
// Added working version of parameterized priority encoder.
|
||||||
|
// David_Harris@Hmc.edu switched to one-hot output
|
||||||
|
//
|
||||||
|
// Purpose: Priority circuit to choose most significant one-hot output
|
||||||
|
//
|
||||||
|
// A component of the Wally configurable RISC-V project.
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||||
|
//
|
||||||
|
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||||
|
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||||
|
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||||
|
// is furnished to do so, subject to the following conditions:
|
||||||
|
//
|
||||||
|
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||||
|
//
|
||||||
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||||
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
///////////////////////////////////////////
|
||||||
|
|
||||||
|
`include "wally-config.vh"
|
||||||
|
|
||||||
|
module prioritythemometer #(parameter N = 8) (
|
||||||
|
input logic [N-1:0] a,
|
||||||
|
output logic [N-1:0] y
|
||||||
|
);
|
||||||
|
|
||||||
|
// generate thermometer code mask
|
||||||
|
genvar i;
|
||||||
|
generate
|
||||||
|
assign y[0] = a[0];
|
||||||
|
for (i=1; i<N; i++) begin
|
||||||
|
assign y[i] = y[i-1] & a[i];
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -39,7 +39,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
|
|||||||
logic AllUsed; // High if the next access causes all RU bits to be 1
|
logic AllUsed; // High if the next access causes all RU bits to be 1
|
||||||
|
|
||||||
// Find the first line not recently used
|
// Find the first line not recently used
|
||||||
prioritycircuit #(.ENTRIES(TLB_ENTRIES), .FINAL_OP("AND")) nru(.a(~RUBits), .FirstPin(1'b1), .y(WriteLines));
|
priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));
|
||||||
|
|
||||||
// Track recently used lines, updating on a CAM Hit or TLB write
|
// Track recently used lines, updating on a CAM Hit or TLB write
|
||||||
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
|
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
|
||||||
|
|||||||
@ -134,6 +134,7 @@ module wallypipelinedhart
|
|||||||
// cpu lsu interface
|
// cpu lsu interface
|
||||||
logic [2:0] Funct3M;
|
logic [2:0] Funct3M;
|
||||||
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
|
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
|
||||||
|
logic [`XLEN-1:0] ReadDataM;
|
||||||
logic [`XLEN-1:0] ReadDataW;
|
logic [`XLEN-1:0] ReadDataW;
|
||||||
logic CommittedM;
|
logic CommittedM;
|
||||||
|
|
||||||
@ -195,7 +196,7 @@ module wallypipelinedhart
|
|||||||
.MemAdrE(MemAdrE),
|
.MemAdrE(MemAdrE),
|
||||||
.MemAdrM(MemAdrM),
|
.MemAdrM(MemAdrM),
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataW),
|
.ReadDataM(ReadDataM),
|
||||||
|
|
||||||
// connected to ahb (all stay the same)
|
// connected to ahb (all stay the same)
|
||||||
.CommitM(CommitM),
|
.CommitM(CommitM),
|
||||||
|
|||||||
512
wally-pipelined/testbench/imperas-boottim.txt
Normal file
512
wally-pipelined/testbench/imperas-boottim.txt
Normal file
@ -0,0 +1,512 @@
|
|||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
|
0000000000000000
|
||||||
@ -46,11 +46,15 @@ module testbench();
|
|||||||
|
|
||||||
string tests32mmu[] = '{
|
string tests32mmu[] = '{
|
||||||
"rv32mmu/WALLY-MMU-SV32", "3000"
|
"rv32mmu/WALLY-MMU-SV32", "3000"
|
||||||
|
//"rv32mmu/WALLY-PMA", "3000",
|
||||||
|
//"rv32mmu/WALLY-PMA", "3000"
|
||||||
};
|
};
|
||||||
|
|
||||||
string tests64mmu[] = '{
|
string tests64mmu[] = '{
|
||||||
"rv64mmu/WALLY-MMU-SV48", "3000",
|
"rv64mmu/WALLY-MMU-SV48", "3000",
|
||||||
"rv64mmu/WALLY-MMU-SV39", "3000"
|
"rv64mmu/WALLY-MMU-SV39", "3000"
|
||||||
|
//"rv64mmu/WALLY-PMA", "3000",
|
||||||
|
//"rv64mmu/WALLY-PMA", "3000"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@ -558,7 +562,7 @@ string tests32f[] = '{
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
string signame, memfilename;
|
string signame, memfilename, romfilename;
|
||||||
|
|
||||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||||
logic UARTSin, UARTSout;
|
logic UARTSin, UARTSout;
|
||||||
@ -604,7 +608,9 @@ string tests32f[] = '{
|
|||||||
end
|
end
|
||||||
// read test vectors into memory
|
// read test vectors into memory
|
||||||
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
|
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
|
||||||
|
romfilename = {"../../imperas-riscv-tests/imperas-boottim.txt"};
|
||||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||||
|
$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
|
||||||
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
|
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
|
||||||
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
|
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
|
||||||
$display("Read memfile %s", memfilename);
|
$display("Read memfile %s", memfilename);
|
||||||
@ -886,6 +892,7 @@ module instrNameDecTB(
|
|||||||
else if (imm == 2) name = "URET";
|
else if (imm == 2) name = "URET";
|
||||||
else if (imm == 258) name = "SRET";
|
else if (imm == 258) name = "SRET";
|
||||||
else if (imm == 770) name = "MRET";
|
else if (imm == 770) name = "MRET";
|
||||||
|
else if (funct7 == 9) name = "SFENCE.VMA";
|
||||||
else name = "ILLEGAL";
|
else name = "ILLEGAL";
|
||||||
10'b1110011_001: name = "CSRRW";
|
10'b1110011_001: name = "CSRRW";
|
||||||
10'b1110011_010: name = "CSRRS";
|
10'b1110011_010: name = "CSRRS";
|
||||||
|
|||||||
@ -27,7 +27,7 @@
|
|||||||
|
|
||||||
module testbench();
|
module testbench();
|
||||||
|
|
||||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3160000; // # of instructions at which to turn on waves in graphical sim
|
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim
|
||||||
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
@ -184,9 +184,12 @@ module testbench();
|
|||||||
scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
|
scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
|
||||||
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
||||||
force dut.hart.ieu.dp.regf.wd3 = regExpected;
|
force dut.hart.ieu.dp.regf.wd3 = regExpected;
|
||||||
// Hack to compensate for QEMU's incorrect MSTATUS
|
// Hack to compensate for QEMU's incorrect MSTATUS (Wally correctly identifies MXL, SXL to be 2 whereas QEMU sets them to an invalid value of 0
|
||||||
end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin
|
end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin
|
||||||
force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000;
|
force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000;
|
||||||
|
// Hack to compensate for QEMU's incorrect SSTATUS (Wally correctly identifies UXL to be 2 whereas QEMU sets it to an invalid value of 0
|
||||||
|
end else if (PCtextW.substr(0,3) == "csrr" && ((PCtextW.substr(10,16) == "sstatus") || (PCtextW.substr(11,17) == "sstatus"))) begin
|
||||||
|
force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'h200000000;
|
||||||
end else release dut.hart.ieu.dp.regf.wd3;
|
end else release dut.hart.ieu.dp.regf.wd3;
|
||||||
// Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature)
|
// Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature)
|
||||||
if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin
|
if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin
|
||||||
@ -265,7 +268,7 @@ module testbench();
|
|||||||
|
|
||||||
// Check PCD, InstrD
|
// Check PCD, InstrD
|
||||||
if (~PCDwrong && ~(dut.hart.ifu.PCD === PCDexpected)) begin
|
if (~PCDwrong && ~(dut.hart.ifu.PCD === PCDexpected)) begin
|
||||||
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected);
|
$display("%0t ps, instr %0d: PCD does not equal PCD expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
InstrMask = InstrDExpected[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
|
InstrMask = InstrDExpected[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user