From b4029a2848a1ee7e466c77e882c3294663c45d11 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Jul 2021 11:06:44 -0500 Subject: [PATCH 01/14] Cleaned up icache and dcache. --- wally-pipelined/src/cache/ICacheCntrl.sv | 9 +++------ wally-pipelined/src/cache/dcache.sv | 18 +++++------------- 2 files changed, 8 insertions(+), 19 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 629ec7cc..35851def 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -141,7 +141,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) logic FetchCountFlag; localparam FetchCountThreshold = WORDSPERLINE - 1; - logic [LOGWPL:0] FetchCount, NextFetchCount; + logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; @@ -195,10 +195,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0; assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit. - // verilator lint_off WIDTH - // *** Bug width is wrong. - assign FetchCountFlag = (FetchCount == FetchCountThreshold); - // verilator lint_on WIDTH + assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); // Next state logic always_comb begin @@ -404,7 +401,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) // to compute the fetch address we need to add the bit shifted // counter output to the address. - flopenr #(LOGWPL+1) + flopenr #(LOGWPL) FetchCountReg(.clk(clk), .reset(reset | CntReset), .en(CntEn), diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 61102b46..82343b86 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -108,7 +108,7 @@ module dcache logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM; logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM; - logic [LOGWPL:0] FetchCount, NextFetchCount; + logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SelMemWriteDataM; logic [2:0] Funct3W; @@ -319,10 +319,7 @@ module dcache assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - // *** fix width later. - // verilator lint_off WIDTH assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; - // verilator lint_on WIDTH mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]), @@ -392,13 +389,8 @@ module dcache assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; - generate - if (`XLEN == 32) begin - assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM; - end else begin - assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM; - end - endgenerate + assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM; + // mux between the CPU's write and the cache fetch. @@ -422,9 +414,9 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); + assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); - flopenr #(LOGWPL+1) + flopenr #(LOGWPL) FetchCountReg(.clk(clk), .reset(reset | CntReset), .en(CntEn), From 9c90b4bdf711ed0b07f45cd01e48aaa05e91f80a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Jul 2021 14:04:56 -0500 Subject: [PATCH 02/14] Fixed bug with the itlb fault not dcache ptw ready state to ready state. --- wally-pipelined/src/cache/dcache.sv | 12 ++++++------ wally-pipelined/src/lsu/lsu.sv | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 82343b86..c79397bf 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -40,7 +40,7 @@ module dcache input logic [1:0] AtomicM, input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. + input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, @@ -56,7 +56,8 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, - input logic ITLBWriteF, + input logic ITLBWriteF, + input logic WalkerInstrPageFaultF, // from ptw input logic SelPTW, input logic WalkerPageFaultM, @@ -378,14 +379,13 @@ module dcache end endgenerate - // *** Coding style. this is just awful. The purpose is to align FetchCount to the - // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. - // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .s(SelEvict), .y(BasePAdrM)); + // if not cacheable the offset bits needs to be sent to the EBU. + // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; @@ -662,7 +662,7 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; - if (ITLBWriteF) begin + if (ITLBWriteF | WalkerInstrPageFaultF) begin NextState = STATE_READY; end diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 50319036..fbde7246 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -319,6 +319,7 @@ module lsu .ITLBWriteF(ITLBWriteF), .SelPTW(SelPTW), .WalkerPageFaultM(WalkerPageFaultM), + .WalkerInstrPageFaultF(WalkerInstrPageFaultF), // AHB connection .AHBPAdr(DCtoAHBPAdrM), From 551e3491afe3233493d8fe094bda7f153a43700c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Jul 2021 14:51:14 -0500 Subject: [PATCH 03/14] Moved the ReadDataW register into the datapath. The StallW from the hazard unit controls this. Previously it was in the dcache and controlled by both the HPTW and hazard unit. This caused an issue when the CPU expected the data to stay constant while stalled, but the HPTW was causing the data to be modified. --- wally-pipelined/regression/wave.do | 178 +++++++++--------- wally-pipelined/src/cache/dcache.sv | 29 ++- wally-pipelined/src/ieu/datapath.sv | 10 +- wally-pipelined/src/ieu/ieu.sv | 5 +- wally-pipelined/src/lsu/lsu.sv | 12 +- wally-pipelined/src/lsu/lsuArb.sv | 3 - .../src/wally/wallypipelinedhart.sv | 5 +- 7 files changed, 123 insertions(+), 119 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 3860decf..b44c2b04 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -2,31 +2,29 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset -add wave -noupdate /testbench/test -add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/hart/SATP_REGW -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/PCtextM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM @@ -158,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/hart/PCF -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/hart/PCE -add wave -noupdate -group PCS /testbench/dut/hart/PCM -add wave -noupdate -group PCS /testbench/PCW +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -253,61 +251,61 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut +add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM @@ -317,16 +315,17 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/StallW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation @@ -352,12 +351,21 @@ add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate /testbench/dut/hart/lsu/hptw/genblk1/PRegEn TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {7778 ns} 0} +WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {41795656 ns} 0} quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -373,4 +381,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {7636 ns} {7946 ns} +WaveRestoreZoom {41795482 ns} {41795818 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index c79397bf..0da202e5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -29,7 +29,7 @@ module dcache (input logic clk, input logic reset, input logic StallM, - input logic StallW, + input logic StallWtoDCache, input logic FlushM, input logic FlushW, @@ -43,7 +43,6 @@ module dcache input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataW, output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, @@ -194,7 +193,7 @@ module dcache flopenr #(7) Funct7WReg(.clk(clk), .reset(reset), - .en(~StallW), + .en(~StallWtoDCache), .d(Funct7M), .q(Funct7W)); @@ -335,7 +334,7 @@ module dcache .HRDATAMasked(ReadDataM)); // This is a confusing point. - // The final read data should be updated only if the CPU's StallW is low + // The final read data should be updated only if the CPU's StallWtoDCache is low // which means the CPU is ready to take data. Or if the CPU just became // busy. Then when we exit CPU_BUSY we want to ensure the data is not // updated, this is ~PreviousCPUBusy. @@ -345,10 +344,6 @@ module dcache flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); - flopen #(`XLEN) ReadDataWReg(.clk(clk), - .en(~StallW), - .d(ReadDataM), - .q(ReadDataW)); // write path @@ -488,7 +483,7 @@ module dcache NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; else NextState = STATE_AMO_UPDATE; @@ -500,7 +495,7 @@ module dcache DCacheAccess = 1'b1; LRUWriteEn = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -515,7 +510,7 @@ module dcache DCacheStall = 1'b1; LRUWriteEn = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -557,7 +552,7 @@ module dcache end STATE_AMO_WRITE: begin SelAMOWrite = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -618,7 +613,7 @@ module dcache //SelAdrM = 1'b1; CommittedM = 1'b1; LRUWriteEn = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -637,7 +632,7 @@ module dcache STATE_MISS_WRITE_WORD_DELAY: begin CommittedM = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -774,7 +769,7 @@ module dcache STATE_CPU_BUSY: begin CommittedM = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -805,7 +800,7 @@ module dcache STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end @@ -815,7 +810,7 @@ module dcache STATE_UNCACHED_READ_DONE: begin CommittedM = 1'b1; SelUncached = 1'b1; - if(StallW) begin + if(StallWtoDCache) begin NextState = STATE_CPU_BUSY; SelAdrM = 1'b1; end diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 1c8e84c8..1e8c7cbf 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -57,8 +57,9 @@ module datapath ( input logic RegWriteW, input logic SquashSCW, input logic [2:0] ResultSrcW, + output logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, - input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, + input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW, // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, output logic [4:0] RdE, RdM, RdW @@ -86,7 +87,7 @@ module datapath ( logic [`XLEN-1:0] ALUResultW; logic [`XLEN-1:0] WriteDataW; logic [`XLEN-1:0] ResultW; - + // Decode stage assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; @@ -137,6 +138,11 @@ module datapath ( assign SCResultW = 0; endgenerate + flopen #(`XLEN) ReadDataWReg(.clk(clk), + .en(~StallW), + .d(ReadDataM), + .q(ReadDataW)); + mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW); /* -----\/----- EXCLUDED -----\/----- // This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage. diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 21aca59b..b23f61b6 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -61,9 +61,10 @@ module ieu ( input logic [`XLEN-1:0] FIntResM, // Writeback stage - input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, + input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW, input logic FWriteIntW, - output logic [4:0] RdW, + output logic [4:0] RdW, + output logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, output logic InstrValidM, // hazards diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index fbde7246..2a46559d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -52,7 +52,7 @@ module lsu input logic [`XLEN-1:0] MemAdrM, input logic [`XLEN-1:0] MemAdrE, input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataW, + output logic [`XLEN-1:0] ReadDataM, // cpu privilege input logic [1:0] PrivilegeModeW, @@ -121,7 +121,6 @@ module lsu logic DTLBMissM; // logic [`XLEN-1:0] PTE; logic DTLBWriteM; - logic [`XLEN-1:0] HPTWReadPTE; logic HPTWStall; logic [`XLEN-1:0] HPTWPAdrE; // logic [`XLEN-1:0] HPTWPAdrM; @@ -164,7 +163,7 @@ module lsu .PageType, .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), - .HPTWReadPTE(HPTWReadPTE), + .HPTWReadPTE(ReadDataM), .HPTWStall(HPTWStall), .TranslationPAdr, .HPTWRead(HPTWRead), @@ -193,7 +192,6 @@ module lsu .CommittedM(CommittedM), .PendingInterruptM(PendingInterruptM), .StallW(StallW), - .ReadDataW(ReadDataW), .DataMisalignedM(DataMisalignedM), .LSUStall(LSUStall), // DCACHE @@ -205,7 +203,6 @@ module lsu .MemAdrEtoDCache(MemAdrEtoDCache), .StallWtoDCache(StallWtoDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), - .ReadDataWfromDCache(ReadDataWfromDCache), .CommittedMfromDCache(CommittedMfromDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache), .DCacheStall(DCacheStall)); @@ -294,7 +291,7 @@ module lsu dcache dcache(.clk(clk), .reset(reset), .StallM(StallM), - .StallW(StallWtoDCache), + .StallWtoDCache(StallWtoDCache), .FlushM(FlushM), .FlushW(FlushWtoDCache), .MemRWM(MemRWMtoDCache), @@ -305,8 +302,7 @@ module lsu .MemPAdrM(MemPAdrM), .VAdr(MemAdrM[11:0]), .WriteDataM(WriteDataM), - .ReadDataW(ReadDataWfromDCache), - .ReadDataM(HPTWReadPTE), + .ReadDataM(ReadDataM), .DCacheStall(DCacheStall), .CommittedM(CommittedMfromDCache), .DCacheMiss, diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 0d08ff7d..0ed4cc30 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -44,7 +44,6 @@ module lsuArb input logic StallW, input logic PendingInterruptM, // to CPU - output logic [`XLEN-1:0] ReadDataW, output logic DataMisalignedM, output logic CommittedM, output logic LSUStall, @@ -63,7 +62,6 @@ module lsuArb // from D Cache input logic CommittedMfromDCache, input logic DataMisalignedMfromDCache, - input logic [`XLEN-1:0] ReadDataWfromDCache, input logic DCacheStall ); @@ -95,7 +93,6 @@ module lsuArb // demux the inputs from LSU to walker or cpu's data port. // works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix - assign ReadDataW = /*SelPTW ? `XLEN'b0 : */ReadDataWfromDCache; // probably can avoid this demux assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. // not clear at all. I think it should be LSUStall from the LSU, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index e6cbaa5a..b84ee6b7 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -134,7 +134,8 @@ module wallypipelinedhart // cpu lsu interface logic [2:0] Funct3M; logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM; - logic [`XLEN-1:0] ReadDataW; + logic [`XLEN-1:0] ReadDataM; + logic [`XLEN-1:0] ReadDataW; logic CommittedM; // AHB ifu interface @@ -195,7 +196,7 @@ module wallypipelinedhart .MemAdrE(MemAdrE), .MemAdrM(MemAdrM), .WriteDataM(WriteDataM), - .ReadDataW(ReadDataW), + .ReadDataM(ReadDataM), // connected to ahb (all stay the same) .CommitM(CommitM), From 98660e0d197197b025e6f9787d960d323bff4835 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 22 Jul 2021 17:52:37 -0400 Subject: [PATCH 04/14] Minor unpacking cleanup --- wally-pipelined/src/fpu/unpacking.sv | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/src/fpu/unpacking.sv b/wally-pipelined/src/fpu/unpacking.sv index 914e9979..a7ec3912 100644 --- a/wally-pipelined/src/fpu/unpacking.sv +++ b/wally-pipelined/src/fpu/unpacking.sv @@ -25,9 +25,9 @@ module unpacking ( assign YSgnE = FmtE ? Y[63] : Y[31]; assign ZSgnE = FmtE ? Z[63] : Z[31]; - assign XExpE = FmtE ? X[62:52] : {X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]}; - assign YExpE = FmtE ? Y[62:52] : {Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]}; - assign ZExpE = FmtE ? Z[62:52] : {Z[30], {3{~Z[30]&~ZExpZero|ZExpMaxE}}, Z[29:23]}; + assign XExpE = FmtE ? X[62:52] : {X[30], {3{~X[30] & XExpNonzero | XExpMaxE}}, X[29:23]}; + assign YExpE = FmtE ? Y[62:52] : {Y[30], {3{~Y[30] & YExpNonzero | YExpMaxE}}, Y[29:23]}; + assign ZExpE = FmtE ? Z[62:52] : {Z[30], {3{~Z[30] & ZExpNonzero | ZExpMaxE}}, Z[29:23]}; /* assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]}; // *** maybe convert to full number of bits here? assign YExpE = FmtE ? Y[62:52] : {3'b0, Y[30:23]}; assign ZExpE = FmtE ? Z[62:52] : {3'b0, Z[30:23]};*/ @@ -40,10 +40,6 @@ module unpacking ( assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23]; assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23]; - assign XManE = {XExpNonzero, XFracE}; - assign YManE = {YExpNonzero, YFracE}; - assign ZManE = {ZExpNonzero, ZFracE}; - assign XExpZero = ~XExpNonzero; assign YExpZero = ~YExpNonzero; assign ZExpZero = ~ZExpNonzero; @@ -52,6 +48,10 @@ module unpacking ( assign YFracZero = ~|YFracE; assign ZFracZero = ~|ZFracE; + assign XManE = {XExpNonzero, XFracE}; + assign YManE = {YExpNonzero, YFracE}; + assign ZManE = {ZExpNonzero, ZFracE}; + assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23]; assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23]; assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23]; From 52faa22774728bb64fc1af5d80816456f5fa23d4 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 22 Jul 2021 20:24:24 -0400 Subject: [PATCH 06/14] include SFENCE.VMA in legal instructions --- wally-pipelined/testbench/testbench-imperas.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 0090a43b..ba778366 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -886,6 +886,7 @@ module instrNameDecTB( else if (imm == 2) name = "URET"; else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; + else if (funct7 == 9) name = "SFENCE.VMA" else name = "ILLEGAL"; 10'b1110011_001: name = "CSRRW"; 10'b1110011_010: name = "CSRRS"; From 3e916da36e4c96576554e7f28e3f79a272edc103 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Jul 2021 19:42:19 -0500 Subject: [PATCH 07/14] Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register, SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select this SavedReadDataM so that the CPU can capture it. --- wally-pipelined/regression/wave.do | 33 ++++++++++++------------ wally-pipelined/src/cache/ICacheCntrl.sv | 7 +---- wally-pipelined/src/cache/dcache.sv | 31 ++++++++++++++++++++-- wally-pipelined/src/lsu/lsu.sv | 8 +++--- 4 files changed, 51 insertions(+), 28 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index b44c2b04..daecfc92 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,11 +7,12 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/PCtextM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM +add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM @@ -127,18 +128,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -314,8 +315,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/StallW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit @@ -365,7 +364,7 @@ add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate /testbench/dut/hart/lsu/hptw/genblk1/PRegEn TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {41795656 ns} 0} +WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {2898 ns} 0} quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -381,4 +380,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {41795482 ns} {41795818 ns} +WaveRestoreZoom {2835 ns} {2995 ns} diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 35851def..3881e9cb 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -115,7 +115,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address? localparam STATE_TLB_MISS = 'h13; localparam STATE_TLB_MISS_DONE = 'h14; - localparam STATE_INSTR_PAGE_FAULT = 'h15; localparam AHBByteLength = `XLEN / 8; @@ -369,7 +368,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) end STATE_TLB_MISS: begin if (WalkerInstrPageFaultF) begin - NextState = STATE_INSTR_PAGE_FAULT; + NextState = STATE_READY; ICacheStallF = 1'b0; end else if (ITLBWriteF) begin NextState = STATE_TLB_MISS_DONE; @@ -380,10 +379,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) STATE_TLB_MISS_DONE: begin NextState = STATE_READY; end - STATE_INSTR_PAGE_FAULT: begin - ICacheStallF = 1'b0; - NextState = STATE_READY; - end default: begin PCMux = 2'b01; NextState = STATE_READY; diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0da202e5..b1edcfa8 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -43,7 +43,7 @@ module dcache input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataM, + output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, output logic DCacheMiss, @@ -60,6 +60,7 @@ module dcache // from ptw input logic SelPTW, input logic WalkerPageFaultM, + output logic [`XLEN-1:0] LSUData, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -147,6 +148,11 @@ module dcache logic SelEvict; logic LRUWriteEn; + + logic CaptureDataM; + logic [`XLEN-1:0] SavedReadDataM; + logic SelSavedReadDataM; + typedef enum {STATE_READY, @@ -331,7 +337,24 @@ module dcache subwordread subwordread(.HRDATA(ReadDataWordMuxM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), - .HRDATAMasked(ReadDataM)); + .HRDATAMasked(LSUData)); + + assign CaptureDataM = ~SelPTW & MemRWM[1]; + + flopen #(`XLEN) + SavedReadDataReg(.clk, + .en(CaptureDataM), + .d(LSUData), + .q(SavedReadDataM)); + + + mux2 #(`XLEN) + ReadDataMMux(.d0(LSUData), + .d1(SavedReadDataM), + .s(SelSavedReadDataM), + .y(ReadDataM)); + + // This is a confusing point. // The final read data should be updated only if the CPU's StallWtoDCache is low @@ -457,6 +480,7 @@ module dcache DCacheAccess = 1'b0; DCacheMiss = 1'b0; LRUWriteEn = 1'b0; + SelSavedReadDataM = 1'b0; case (CurrState) STATE_READY: begin @@ -659,6 +683,9 @@ module dcache if (ITLBWriteF | WalkerInstrPageFaultF) begin NextState = STATE_READY; + // this signal is gross. It is used to select the saved read data m when the + // CPU was stalled for an itlb miss with a simultaneous load. + SelSavedReadDataM = 1'b1; end // return to ready if page table walk completed. diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 2a46559d..7afb2499 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -148,8 +148,9 @@ module lsu logic PendingInterruptMtoDCache; logic FlushWtoDCache; logic WalkerPageFaultM; - - + + logic [`XLEN-1:0] LSUData; + hptw hptw( .clk(clk), .reset(reset), @@ -163,7 +164,7 @@ module lsu .PageType, .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), - .HPTWReadPTE(ReadDataM), + .HPTWReadPTE(LSUData), .HPTWStall(HPTWStall), .TranslationPAdr, .HPTWRead(HPTWRead), @@ -303,6 +304,7 @@ module lsu .VAdr(MemAdrM[11:0]), .WriteDataM(WriteDataM), .ReadDataM(ReadDataM), + .LSUData(LSUData), .DCacheStall(DCacheStall), .CommittedM(CommittedMfromDCache), .DCacheMiss, From 5d2b30e33294531f19d4e61b2787e444ea8772c8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 23 Jul 2021 08:11:15 -0400 Subject: [PATCH 08/14] Removed LEVELx states from HPTW --- wally-pipelined/src/mmu/hptw.sv | 92 ++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index b3bff0ea..845f495d 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -65,10 +65,10 @@ module hptw logic [`XLEN-1:0] TranslationVAdr; - typedef enum {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0, - LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1, - LEVEL2_SET_ADR, LEVEL2_READ, LEVEL2, - LEVEL3_SET_ADR, LEVEL3_READ, LEVEL3, + typedef enum {L0_ADR, L0_RD, + L1_ADR, L1_RD, + L2_ADR, L2_RD, + L3_ADR, L3_RD, LEAF, IDLE, FAULT} statetype; statetype WalkerState, NextWalkerState, InitialWalkerState; @@ -97,7 +97,7 @@ module hptw // Enable and select signals based on states assign StartWalk = (WalkerState == IDLE) & TLBMiss; - assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ); + assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD); assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk; @@ -111,10 +111,10 @@ module hptw flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType); always_comb case (WalkerState) - LEVEL3: NextPageType = 2'b11; // terapage - LEVEL2: NextPageType = 2'b10; // gigapage - LEVEL1: NextPageType = 2'b01; // megapage - LEVEL0: NextPageType = 2'b00; // kilopage + L3_RD: NextPageType = 2'b11; // terapage + L2_RD: NextPageType = 2'b10; // gigapage + L1_RD: NextPageType = 2'b01; // megapage + L0_RD: NextPageType = 2'b00; // kilopage default: NextPageType = PageType; endcase @@ -122,36 +122,36 @@ module hptw if (`XLEN==32) begin // RV32 logic [9:0] VPN; logic [`PPN_BITS-1:0] PPN; - assign VPN = ((WalkerState == LEVEL1_SET_ADR) | (WalkerState == LEVEL1_READ)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state - assign PPN = ((WalkerState == LEVEL1_SET_ADR) | (WalkerState == LEVEL1_READ)) ? BasePageTablePPN : CurrentPPN; + assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state + assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; assign TranslationPAdr = {PPN, VPN, 2'b00}; end else begin // RV64 logic [8:0] VPN; logic [`PPN_BITS-1:0] PPN; always_comb case (WalkerState) // select VPN field based on HPTW state - LEVEL3_SET_ADR, LEVEL3_READ: VPN = TranslationVAdr[47:39]; - LEVEL3, LEVEL2_SET_ADR, LEVEL2_READ: VPN = TranslationVAdr[38:30]; - LEVEL2, LEVEL1_SET_ADR, LEVEL1_READ: VPN = TranslationVAdr[29:21]; + L3_ADR, L3_RD: VPN = TranslationVAdr[47:39]; + L2_ADR, L2_RD: VPN = TranslationVAdr[38:30]; + L1_ADR, L1_RD: VPN = TranslationVAdr[29:21]; default: VPN = TranslationVAdr[20:12]; endcase - assign PPN = ((WalkerState == LEVEL3_SET_ADR) | (WalkerState == LEVEL3_READ) | - (SvMode != `SV48 & ((WalkerState == LEVEL2_SET_ADR) | (WalkerState == LEVEL2_READ)))) ? BasePageTablePPN : CurrentPPN; + assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | + (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN; assign TranslationPAdr = {PPN, VPN, 3'b000}; end // Initial state and misalignment for RV32/64 if (`XLEN == 32) begin - assign InitialWalkerState = LEVEL1_SET_ADR; + assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 - assign Misaligned = ((WalkerState == LEVEL1) & MegapageMisaligned); + assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned; - assign InitialWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADR : LEVEL2_SET_ADR; + assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR; assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0 - assign Misaligned = ((WalkerState == LEVEL3) & TerapageMisaligned) | ((WalkerState == LEVEL2) & GigapageMisaligned) | ((WalkerState == LEVEL1) & MegapageMisaligned); + assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned); end // Page Table Walker FSM @@ -164,29 +164,37 @@ module hptw case (WalkerState) IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; - LEVEL3_SET_ADR: NextWalkerState = LEVEL3_READ; - LEVEL3_READ: if (HPTWStall) NextWalkerState = LEVEL3_READ; - else NextWalkerState = LEVEL3; - LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; - else if (ValidNonLeafPTE) NextWalkerState = LEVEL2_SET_ADR; + L3_ADR: NextWalkerState = L3_RD; // first access in SV48 + L3_RD: if (HPTWStall) NextWalkerState = L3_RD; + else NextWalkerState = L2_ADR; +// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; +// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR; +// else NextWalkerState = FAULT; + L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39 + else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages + else if (ValidNonLeafPTE) NextWalkerState = L2_RD; + else NextWalkerState = FAULT; + L2_RD: if (HPTWStall) NextWalkerState = L2_RD; + else NextWalkerState = L1_ADR; +// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; +// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR; +// else NextWalkerState = FAULT; + L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32 + else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages + else if (ValidNonLeafPTE) NextWalkerState = L1_RD; + else NextWalkerState = FAULT; + L1_RD: if (HPTWStall) NextWalkerState = L1_RD; + else NextWalkerState = L0_ADR; +// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; +// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR; +// else NextWalkerState = FAULT; + L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = FAULT; - LEVEL2_SET_ADR: NextWalkerState = LEVEL2_READ; - LEVEL2_READ: if (HPTWStall) NextWalkerState = LEVEL2_READ; - else NextWalkerState = LEVEL2; - LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; - else if (ValidNonLeafPTE) NextWalkerState = LEVEL1_SET_ADR; - else NextWalkerState = FAULT; - LEVEL1_SET_ADR: NextWalkerState = LEVEL1_READ; - LEVEL1_READ: if (HPTWStall) NextWalkerState = LEVEL1_READ; - else NextWalkerState = LEVEL1; - LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; - else if (ValidNonLeafPTE) NextWalkerState = LEVEL0_SET_ADR; - else NextWalkerState = FAULT; - LEVEL0_SET_ADR: NextWalkerState = LEVEL0_READ; - LEVEL0_READ: if (HPTWStall) NextWalkerState = LEVEL0_READ; - else NextWalkerState = LEVEL0; - LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF; - else NextWalkerState = FAULT; + L0_RD: if (HPTWStall) NextWalkerState = L0_RD; + else NextWalkerState = LEAF; +// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF; +// else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; FAULT: NextWalkerState = IDLE; default: begin From f3579032bdd3e812be5ec94716f37d840f28437f Mon Sep 17 00:00:00 2001 From: kipmacsaigoren Date: Fri, 23 Jul 2021 11:57:58 -0500 Subject: [PATCH 09/14] Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's --- wally-pipelined/src/mmu/hptw.sv | 12 ++--- wally-pipelined/src/mmu/pmpadrdec.sv | 23 +++------ wally-pipelined/src/mmu/pmpchecker.sv | 2 +- .../{prioritycircuit.sv => priorityonehot.sv} | 21 +++----- .../src/mmu/prioritythermometer.sv | 50 +++++++++++++++++++ wally-pipelined/src/mmu/tlblru.sv | 2 +- 6 files changed, 70 insertions(+), 40 deletions(-) rename wally-pipelined/src/mmu/{prioritycircuit.sv => priorityonehot.sv} (78%) create mode 100644 wally-pipelined/src/mmu/prioritythermometer.sv diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index 845f495d..fd7cee43 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -48,6 +48,12 @@ module hptw output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults ); + typedef enum {L0_ADR, L0_RD, + L1_ADR, L1_RD, + L2_ADR, L2_RD, + L3_ADR, L3_RD, + LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors + generate if (`MEM_VIRTMEM) begin logic DTLBWalk; // register TLBs translation miss requests @@ -64,12 +70,6 @@ module hptw logic [`SVMODE_BITS-1:0] SvMode; logic [`XLEN-1:0] TranslationVAdr; - - typedef enum {L0_ADR, L0_RD, - L1_ADR, L1_RD, - L2_ADR, L2_RD, - L3_ADR, L3_RD, - LEAF, IDLE, FAULT} statetype; statetype WalkerState, NextWalkerState, InitialWalkerState; // Extract bits from CSRs and inputs diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv index 0fe2b2d7..61816782 100644 --- a/wally-pipelined/src/mmu/pmpadrdec.sv +++ b/wally-pipelined/src/mmu/pmpadrdec.sv @@ -67,9 +67,7 @@ module pmpadrdec ( assign TORMatch = PAgePMPAdrIn && PAltPMPAdr; // Naturally aligned regions - - // verilator lint_off UNOPTFLAT - logic [`PA_BITS-1:0] Mask; + logic [`PA_BITS-1:0] NAMask; //genvar i; // create a mask of which bits to ignore @@ -80,23 +78,14 @@ module pmpadrdec ( // assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore // end // endgenerate - prioritycircuit #(.ENTRIES(`PA_BITS-2), .FINAL_OP("NONE")) maskgen(.a(~PMPAdr[`PA_BITS-3:0]), .FirstPin(AdrMode==NAPOT), .y(Mask[`PA_BITS-1:2])); - assign Mask[1:0] = 2'b11; - // *** possible experiments: - /* PA < PMP addr could be in its own module, - preeserving hierarchy so we can know if this is the culprit on the critical path - Should take logarthmic time, so more like 6 levels than 40 should be expected + assign NAMask[1:0] = {2'b11}; - update mask generation - Should be concurrent with the subtraction/comparison - if one is the critical path, the other shouldn't be which makes us think the mask generation is the culprit. + prioritythemometer #(`PA_BITS-2) namaskgen( + .a({PMPAdr[`PA_BITS-4:0], (AdrMode == NAPOT)}), + .y(NAMask[`PA_BITS-1:2])); - Hopefully just use the priority circuit here - */ - // verilator lint_on UNOPTFLAT - - assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask); + assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | NAMask); assign Match = (AdrMode == TOR) ? TORMatch : (AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch : diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index eac4cc47..7dc37163 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -69,7 +69,7 @@ module pmpchecker ( .PAgePMPAdrOut(PAgePMPAdr), .FirstMatch, .Match, .Active, .L, .X, .W, .R); - prioritycircuit #(.ENTRIES(`PMP_ENTRIES), .FINAL_OP("AND")) pmppriority(.a(Match), .FirstPin(1'b1), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit. + priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit. // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; diff --git a/wally-pipelined/src/mmu/prioritycircuit.sv b/wally-pipelined/src/mmu/priorityonehot.sv similarity index 78% rename from wally-pipelined/src/mmu/prioritycircuit.sv rename to wally-pipelined/src/mmu/priorityonehot.sv index df44b35f..75825dc4 100644 --- a/wally-pipelined/src/mmu/prioritycircuit.sv +++ b/wally-pipelined/src/mmu/priorityonehot.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// prioritycircuit.sv +// priorityonehot.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Modified: Teo Ene 15 Apr 2021: @@ -30,31 +30,22 @@ `include "wally-config.vh" -module prioritycircuit #(parameter ENTRIES = 8, - parameter FINAL_OP = "AND") ( +module priorityonehot #(parameter ENTRIES = 8) ( input logic [ENTRIES-1:0] a, - input logic FirstPin, output logic [ENTRIES-1:0] y ); - // verilator lint_off UNOPTFLAT + logic [ENTRIES-1:0] nolower; // generate thermometer code mask genvar i; generate - assign nolower[0] = FirstPin; + assign nolower[0] = 1'b1; for (i=1; i Date: Fri, 23 Jul 2021 14:00:44 -0400 Subject: [PATCH 10/14] testbench workaround for QEMU's SSTATUS XLEN bits --- wally-pipelined/testbench/testbench-linux.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 79827c4f..64b0483d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ module testbench(); - parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3160000; // # of instructions at which to turn on waves in graphical sim + parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can) /////////////////////////////////////////////////////////////////////////////// @@ -184,9 +184,12 @@ module testbench(); scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); force dut.hart.ieu.dp.regf.wd3 = regExpected; - // Hack to compensate for QEMU's incorrect MSTATUS + // Hack to compensate for QEMU's incorrect MSTATUS (Wally correctly identifies MXL, SXL to be 2 whereas QEMU sets them to an invalid value of 0 end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000; + // Hack to compensate for QEMU's incorrect SSTATUS (Wally correctly identifies UXL to be 2 whereas QEMU sets it to an invalid value of 0 + end else if (PCtextW.substr(0,3) == "csrr" && ((PCtextW.substr(10,16) == "sstatus") || (PCtextW.substr(11,17) == "sstatus"))) begin + force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'h200000000; end else release dut.hart.ieu.dp.regf.wd3; // Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature) if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin @@ -265,7 +268,7 @@ module testbench(); // Check PCD, InstrD if (~PCDwrong && ~(dut.hart.ifu.PCD === PCDexpected)) begin - $display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected); + $display("%0t ps, instr %0d: PCD does not equal PCD expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected); `ERROR end InstrMask = InstrDExpected[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF; From 381a93b45b61cbec9208d44d7b8c15be81a4485d Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 23 Jul 2021 15:55:08 -0400 Subject: [PATCH 13/14] added sfence to legal instructions, zeroed out rom file to populate for tests --- wally-pipelined/testbench/imperas-boottim.txt | 512 ++++++++++++++++++ .../testbench/testbench-imperas.sv | 8 +- 2 files changed, 518 insertions(+), 2 deletions(-) create mode 100644 wally-pipelined/testbench/imperas-boottim.txt diff --git a/wally-pipelined/testbench/imperas-boottim.txt b/wally-pipelined/testbench/imperas-boottim.txt new file mode 100644 index 00000000..3e34cef6 --- /dev/null +++ b/wally-pipelined/testbench/imperas-boottim.txt @@ -0,0 +1,512 @@ +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 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+0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index ba778366..a47faf20 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -51,6 +51,8 @@ module testbench(); string tests64mmu[] = '{ "rv64mmu/WALLY-MMU-SV48", "3000", "rv64mmu/WALLY-MMU-SV39", "3000" + //"rv64mmu/WALLY-PMA", "3000", + //"rv64mmu/WALLY-PMA", "3000" }; @@ -558,7 +560,7 @@ string tests32f[] = '{ end end - string signame, memfilename; + string signame, memfilename, romfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -604,7 +606,9 @@ string tests32f[] = '{ end // read test vectors into memory memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; + romfilename = {"../../imperas-riscv-tests/imperas-boottim.txt"}; $readmemh(memfilename, dut.uncore.dtim.RAM); + $readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM); ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"}; $display("Read memfile %s", memfilename); @@ -886,7 +890,7 @@ module instrNameDecTB( else if (imm == 2) name = "URET"; else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; - else if (funct7 == 9) name = "SFENCE.VMA" + else if (funct7 == 9) name = "SFENCE.VMA"; else name = "ILLEGAL"; 10'b1110011_001: name = "CSRRW"; 10'b1110011_010: name = "CSRRS"; From 3008111bcd0d701ab866db3cf8fc4b1268ad5ede Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 23 Jul 2021 16:02:42 -0400 Subject: [PATCH 14/14] added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet --- wally-pipelined/testbench/testbench-imperas.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index a47faf20..b3ccaf58 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -46,6 +46,8 @@ module testbench(); string tests32mmu[] = '{ "rv32mmu/WALLY-MMU-SV32", "3000" + //"rv32mmu/WALLY-PMA", "3000", + //"rv32mmu/WALLY-PMA", "3000" }; string tests64mmu[] = '{