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Merge branch 'main' of github.com:ross144/cvw

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This commit is contained in:
Ross Thompson 2023-03-28 16:22:26 -05:00
commit 6b58cb8d65
5 changed files with 9 additions and 7 deletions
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2
src/cache/cachefsm.sv vendored
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@ -135,7 +135,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
end end
// com back to CPU // com back to CPU
assign CacheCommitted = CurrState != STATE_READY; assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
(CurrState == STATE_FETCH) | (CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITEBACK) |

5
src/ebu/ahbcacheinterface.sv
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@ -33,7 +33,8 @@ module ahbcacheinterface #(
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter AHBWLOGBWPL, // Log2 of ^ parameter AHBWLOGBWPL, // Log2 of ^
parameter LINELEN, // Number of bits in cacheline parameter LINELEN, // Number of bits in cacheline
parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
parameter READ_ONLY_CACHE
)( )(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface controls // bus interface controls
@ -115,7 +116,7 @@ module ahbcacheinterface #(
flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);

5
src/ebu/buscachefsm.sv
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@ -33,7 +33,8 @@
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module buscachefsm #( module buscachefsm #(
parameter BeatCountThreshold, // Largest beat index parameter BeatCountThreshold, // Largest beat index
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE
parameter READ_ONLY_CACHE
)( )(
input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
@ -121,7 +122,7 @@ module buscachefsm #(
(CurrState == DATA_PHASE) | (CurrState == DATA_PHASE) |
(CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_FETCH & ~HREADY) |
(CurrState == CACHE_WRITEBACK & ~HREADY); (CurrState == CACHE_WRITEBACK & ~HREADY);
assign BusCommitted = CurrState != ADR_PHASE; assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3);
// AHB bus interface // AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) |

2
src/ifu/ifu.sv
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@ -251,7 +251,7 @@ module ifu (
.NextSet(PCSpillNextF[11:0]), .NextSet(PCSpillNextF[11:0]),
.PAdr(PCPF), .PAdr(PCPF),
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),

2
src/lsu/lsu.sv
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@ -275,7 +275,7 @@ module lsu (
.FetchBuffer, .CacheBusRW, .FetchBuffer, .CacheBusRW,
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),