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Changed logging enables, debug mode in sim.

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This commit is contained in:
Limnanthes Serafini 2023-04-04 23:49:35 -07:00
parent 8f3413f0d5
commit 6abd4ee1b7
2 changed files with 43 additions and 36 deletions
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49
bin/CacheSim.py
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@ -8,7 +8,7 @@ import math
import argparse import argparse
import os import os
debug = True fulltrace = False
class CacheLine: class CacheLine:
def __init__(self): def __init__(self):
@ -24,8 +24,6 @@ class CacheLine:
def __repr__(self): def __repr__(self):
return self.__str__() return self.__str__()
class Cache: class Cache:
def __init__(self, numsets, numways, addrlen, taglen): def __init__(self, numsets, numways, addrlen, taglen):
self.numways = numways self.numways = numways
@ -177,33 +175,30 @@ if __name__ == "__main__":
lninfo = ln.split() lninfo = ln.split()
if len(lninfo) < 3: #non-address line if len(lninfo) < 3: #non-address line
if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'): if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'):
#currently BEGIN and END traces aren't being recorded correctly # currently BEGIN and END traces aren't being recorded correctly
#trying TRAIN clears instead # trying TRAIN clears instead
cache.invalidate() # a new test is starting, so 'empty' the cache cache.invalidate() # a new test is starting, so 'empty' the cache
cache.clear_pLRU() cache.clear_pLRU()
if debug: if fulltrace:
print("new test?") print("New Test")
else: else:
if len(lninfo[0]) >= (cache.addrlen/4): #more hacking around the logging issues if lninfo[1] == 'F':
if lninfo[1] == 'F': cache.flush()
cache.flush() if fulltrace:
if debug: print("F")
print("flush") elif lninfo[1] == 'I':
elif lninfo[1] == 'I': cache.invalidate()
cache.invalidate() if fulltrace:
if debug: print("I")
print("inval") else:
else: addr = int(lninfo[0], 16)
addr = int(lninfo[0], 16) iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' result = cache.cacheaccess(addr, iswrite)
result = cache.cacheaccess(addr, iswrite) if fulltrace:
if debug: tag, setnum, offset = cache.splitaddr(addr)
tag, setnum, offset = cache.splitaddr(addr) print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result) if not result == lninfo[2]:
if not result == lninfo[2]: print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result)
print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result)
if debug:
break # breaking after the first mismatch makes for easier debugging

30
testbench/testbench.sv
View File

@ -30,8 +30,8 @@
`define PrintHPMCounters 0 `define PrintHPMCounters 0
`define BPRED_LOGGER 0 `define BPRED_LOGGER 0
`define I_CACHE_ADDR_LOGGER 0 `define I_CACHE_ADDR_LOGGER 1
`define D_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 1
module testbench; module testbench;
parameter DEBUG=0; parameter DEBUG=0;
@ -560,7 +560,13 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
logic Enable; logic Enable;
assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
// this version of enable does create repeated instructions (i.e, when there's a stall)
// but! it allows us to correctly log evictions
// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK
// for now at least
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn;
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
initial begin initial begin
@ -600,15 +606,21 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
"NULL"; "NULL";
assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) & // assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & // ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
(AccessTypeString != "NULL"); // (AccessTypeString != "NULL");
// this version of enable does create repeated instructions (i.e, when there's a stall)
// but! it allows us to correctly log evictions
// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK
// for now at least
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn;
initial begin initial begin
LogFile = $psprintf("DCache.log"); LogFile = $psprintf("DCache.log");
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename); $fwrite(file, "BEGIN %s\n", memfilename);
end end
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);