From 6abd4ee1b74f08e905df236969c04b1cf1253361 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Tue, 4 Apr 2023 23:49:35 -0700 Subject: [PATCH] Changed logging enables, debug mode in sim. --- bin/CacheSim.py | 49 +++++++++++++++++++----------------------- testbench/testbench.sv | 30 ++++++++++++++++++-------- 2 files changed, 43 insertions(+), 36 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 44b773c5..4a23fb7a 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -8,7 +8,7 @@ import math import argparse import os -debug = True +fulltrace = False class CacheLine: def __init__(self): @@ -23,8 +23,6 @@ class CacheLine: def __repr__(self): return self.__str__() - - class Cache: def __init__(self, numsets, numways, addrlen, taglen): @@ -177,33 +175,30 @@ if __name__ == "__main__": lninfo = ln.split() if len(lninfo) < 3: #non-address line if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'): - #currently BEGIN and END traces aren't being recorded correctly - #trying TRAIN clears instead + # currently BEGIN and END traces aren't being recorded correctly + # trying TRAIN clears instead cache.invalidate() # a new test is starting, so 'empty' the cache cache.clear_pLRU() - if debug: - print("new test?") + if fulltrace: + print("New Test") else: - if len(lninfo[0]) >= (cache.addrlen/4): #more hacking around the logging issues - if lninfo[1] == 'F': - cache.flush() - if debug: - print("flush") - elif lninfo[1] == 'I': - cache.invalidate() - if debug: - print("inval") - else: - addr = int(lninfo[0], 16) - iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' - result = cache.cacheaccess(addr, iswrite) - if debug: - tag, setnum, offset = cache.splitaddr(addr) - print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result) - if not result == lninfo[2]: - print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) - if debug: - break # breaking after the first mismatch makes for easier debugging + if lninfo[1] == 'F': + cache.flush() + if fulltrace: + print("F") + elif lninfo[1] == 'I': + cache.invalidate() + if fulltrace: + print("I") + else: + addr = int(lninfo[0], 16) + iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' + result = cache.cacheaccess(addr, iswrite) + if fulltrace: + tag, setnum, offset = cache.splitaddr(addr) + print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result) + if not result == lninfo[2]: + print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 00a43560..aae777da 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,8 +30,8 @@ `define PrintHPMCounters 0 `define BPRED_LOGGER 0 -`define I_CACHE_ADDR_LOGGER 0 -`define D_CACHE_ADDR_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 1 +`define D_CACHE_ADDR_LOGGER 1 module testbench; parameter DEBUG=0; @@ -560,7 +560,13 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger string LogFile; logic resetD, resetEdge; logic Enable; - assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; + // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; + + // this version of enable does create repeated instructions (i.e, when there's a stall) + // but! it allows us to correctly log evictions + // and re-accessing the same portion of memory just generates another hit, so the duplicates are OK + // for now at least + assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin @@ -600,15 +606,21 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : "NULL"; - assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) & - ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & - (AccessTypeString != "NULL"); + // assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) & + // ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & + // (AccessTypeString != "NULL"); + + // this version of enable does create repeated instructions (i.e, when there's a stall) + // but! it allows us to correctly log evictions + // and re-accessing the same portion of memory just generates another hit, so the duplicates are OK + // for now at least + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn; initial begin - LogFile = $psprintf("DCache.log"); + LogFile = $psprintf("DCache.log"); file = $fopen(LogFile, "w"); - $fwrite(file, "BEGIN %s\n", memfilename); - end + $fwrite(file, "BEGIN %s\n", memfilename); + end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);