From 68745d40f2d80a83ff188c8422f05a86e5b96710 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 12 Dec 2021 17:21:44 -0600 Subject: [PATCH] Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. --- fpga/constraints/debug2.xdc | 6 +++-- fpga/debug_notes.org | 16 ++++++++++++ fpga/generator/Makefile | 2 +- fpga/trigger_issues.tsm | 36 ++++++++++++++++++++++++++ wally-pipelined/src/cache/icachefsm.sv | 2 +- 5 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 fpga/debug_notes.org create mode 100644 fpga/trigger_issues.tsm diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 9cb695b9..917c2b6d 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -389,7 +389,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/hart/hzu/Br create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe88] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] -connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheMp ]] +connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe89] @@ -411,10 +411,11 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe92] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]] +# StallW is StallM. trying to connect to StallW causes issues. create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe93] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] -connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallW ]] +connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe94] @@ -445,3 +446,4 @@ create_debug_port u_ila_0 probe set_property port_width 24 [get_debug_ports u_ila_0/probe99] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]] + diff --git a/fpga/debug_notes.org b/fpga/debug_notes.org new file mode 100644 index 00000000..84952d8c --- /dev/null +++ b/fpga/debug_notes.org @@ -0,0 +1,16 @@ +* December 12, 2021 +Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY +InstrM = f884_3803 +PCM = ffff_ffff_8030_8004 + +Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY +InstrM = 0207_ba03 +PCM = ffff_ffff_8034_89fe + +Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY +InstrM = 0016_c383 +PCM = ffff_ffff_8030_7504 + +Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY +InstrM = 0006_a703 +PCM = ffff_ffff_8028_fa02 diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index c65e522f..bf9402e1 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -3,7 +3,7 @@ dst := IP all: FPGA FPGA: IP - vivado -mode batch -source wally.tcl | tee wally.log + vivado -mode batch -source wally.tcl 2>&1 | tee wally.log IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr4.log \ diff --git a/fpga/trigger_issues.tsm b/fpga/trigger_issues.tsm new file mode 100644 index 00000000..421c0a7a --- /dev/null +++ b/fpga/trigger_issues.tsm @@ -0,0 +1,36 @@ +################################################## +# +# For info on creating trigger state machines: +# 1) In the main Vivado menu bar, select +# Window > Language Templates +# 2) In the Templates window, select +# Debug > Trigger State Machine +# 3) Refer to the entry 'Info' for an overview +# of the trigger state machine language. +# +# More information can be found in this document: +# +# Vivado Design Suite User Guide: Programming +# and Debugging (UG908) +# +################################################## +state state_reset: + if(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then + reset_counter $counter0; + goto state_begin_count; + else + goto state_reset; + endif + +state state_begin_count: + if($counter0 == 16'h0064) then + goto state_trigger; + elseif(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then + increment_counter $counter0; + goto state_begin_count; + else + goto state_reset; + endif + +state state_trigger: + trigger; diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index fa0268bb..433328ab 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -114,7 +114,7 @@ module icachefsm STATE_CPU_BUSY_SPILL } statetype; - statetype CurrState, NextState; + (* mark_debug = "true" *) statetype CurrState, NextState; logic PreCntEn; // the FSM is always runing, do not stall.