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Progress on arty a7 board.

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This commit is contained in:
Ross Thompson 2023-04-13 17:57:12 -05:00
parent 1861ca8c86
commit 679dc7d73b
2 changed files with 31 additions and 8 deletions
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16
fpga/generator/Makefile
View File

@ -1,9 +1,9 @@
dst := IP dst := IP
sdc_src := ~/repos/sdc.tar.gz sdc_src := ~/repos/sdc.tar.gz
# vcu118 # vcu118
export XILINX_PART := xcvu9p-flga2104-2L-e #export XILINX_PART := xcvu9p-flga2104-2L-e
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 #export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
export board := vcu118 #export board := vcu118
# vcu108 # vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e #export XILINX_PART := xcvu095-ffva2104-2-e
@ -11,22 +11,22 @@ export board := vcu118
#export board := vcu108 #export board := vcu108
# Arty A7 # Arty A7
#export XILINX_PART := xc7a100tcsg324-1 export XILINX_PART := xc7a100tcsg324-1
#export XILINX_BOARD := ArtyA7 export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
#export board := ArtyA7 export board := ArtyA7
all: FPGA all: FPGA
FPGA: PreProcessFiles IP SDC FPGA: PreProcessFiles IP SDC
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
IP: $(dst)/xlnx_proc_sys_reset.log \ #IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr4-$(board).log \ $(dst)/xlnx_ddr4-$(board).log \
$(dst)/xlnx_ddr3-ArtyA7.log \ $(dst)/xlnx_ddr3-ArtyA7.log \
$(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log $(dst)/xlnx_ahblite_axi_bridge.log
#IP: $(dst)/xlnx_proc_sys_reset.log \ IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr3-ArtyA7.log \ $(dst)/xlnx_ddr3-ArtyA7.log \
$(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log $(dst)/xlnx_ahblite_axi_bridge.log

23
fpga/generator/xlnx_ddr3-ArtyA7.tcl Normal file
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@ -0,0 +1,23 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_ddr3
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
# really just these two lines which change
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
exec ls ../xlnx_ddr3-artya7-mig.prj
exec ls ./IP/$ipName.srcs/sources_1/ip/$ipName
exec cp ../xlnx_ddr3-artya7-mig.prj ./IP/$ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1