From 679dc7d73b7718ddf013bc30f8252ef87fcbcc5a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 13 Apr 2023 17:57:12 -0500
Subject: [PATCH] Progress on arty a7 board.

---
 fpga/generator/Makefile             | 16 ++++++++--------
 fpga/generator/xlnx_ddr3-ArtyA7.tcl | 23 +++++++++++++++++++++++
 2 files changed, 31 insertions(+), 8 deletions(-)
 create mode 100644 fpga/generator/xlnx_ddr3-ArtyA7.tcl

diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index c760f50f..2d6a3a14 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -1,9 +1,9 @@
 dst := IP
 sdc_src := ~/repos/sdc.tar.gz
 # vcu118
-export XILINX_PART := xcvu9p-flga2104-2L-e
-export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
-export board := vcu118
+#export XILINX_PART := xcvu9p-flga2104-2L-e
+#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
+#export board := vcu118
 
 # vcu108
 #export XILINX_PART := xcvu095-ffva2104-2-e
@@ -11,22 +11,22 @@ export board := vcu118
 #export board := vcu108
 
 # Arty A7
-#export XILINX_PART := xc7a100tcsg324-1
-#export XILINX_BOARD := ArtyA7
-#export board := ArtyA7
+export XILINX_PART := xc7a100tcsg324-1
+export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
+export board := ArtyA7
 
 all: FPGA
 
 FPGA: PreProcessFiles IP SDC
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
 
-IP: $(dst)/xlnx_proc_sys_reset.log \
+#IP: $(dst)/xlnx_proc_sys_reset.log \
 	$(dst)/xlnx_ddr4-$(board).log \
 	$(dst)/xlnx_ddr3-ArtyA7.log \
 	$(dst)/xlnx_axi_clock_converter.log \
 	 $(dst)/xlnx_ahblite_axi_bridge.log
 
-#IP: $(dst)/xlnx_proc_sys_reset.log \
+IP: $(dst)/xlnx_proc_sys_reset.log \
 	$(dst)/xlnx_ddr3-ArtyA7.log \
 	$(dst)/xlnx_axi_clock_converter.log \
 	 $(dst)/xlnx_ahblite_axi_bridge.log
diff --git a/fpga/generator/xlnx_ddr3-ArtyA7.tcl b/fpga/generator/xlnx_ddr3-ArtyA7.tcl
new file mode 100644
index 00000000..50418900
--- /dev/null
+++ b/fpga/generator/xlnx_ddr3-ArtyA7.tcl
@@ -0,0 +1,23 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+
+set ipName xlnx_ddr3
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+# really just these two lines which change
+create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
+
+exec ls ../xlnx_ddr3-artya7-mig.prj
+exec ls ./IP/$ipName.srcs/sources_1/ip/$ipName
+exec cp ../xlnx_ddr3-artya7-mig.prj ./IP/$ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
+
+set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1