From 6769f0cb4370c3bf2f13fe47722cae110a7ec1cc Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Apr 2022 16:53:10 +0000 Subject: [PATCH] Added comments in fcvt --- pipelined/regression/wkdir/README | 0 pipelined/src/fpu/fcvtfp.sv | 8 +++++++- pipelined/src/fpu/fcvtint.sv | 4 ++++ 3 files changed, 11 insertions(+), 1 deletion(-) delete mode 100644 pipelined/regression/wkdir/README diff --git a/pipelined/regression/wkdir/README b/pipelined/regression/wkdir/README deleted file mode 100644 index e69de29b..00000000 diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv index e93822ee..fb8e1ad9 100644 --- a/pipelined/src/fpu/fcvtfp.sv +++ b/pipelined/src/fpu/fcvtfp.sv @@ -30,11 +30,17 @@ module cvtfp ( logic [31:0] DSRes; // double to single precision result + // add support for all formats + // consider reordering code blocks so upconverting is in one region of the file + // and downconverting is in the other region. /////////////////////////////////////////////////////////////////////////////// - // LZC + // LZC: Leading Zero Counter /////////////////////////////////////////////////////////////////////////////// + // *** consider sharing this with fcvtint + // *** emphasize parallel structure between the two + // *** add a priorityencoder module to generic (similar to priorityonehot) and use it // LZC - find the first 1 in the input's mantissa logic [8:0] i,NormCnt; diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv index d394d7c3..6a668699 100644 --- a/pipelined/src/fpu/fcvtint.sv +++ b/pipelined/src/fpu/fcvtint.sv @@ -61,6 +61,10 @@ module fcvt ( // fcvt.d.l = 100 // fcvt.d.lu = 110 // {long, unsigned, to int} + + // *** revisit this module, explain in more depth + // should the int to fp and fp to int paths be separated? + // add support for all formats // calculate signals based off the input and output's size assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);