From 66e53929cefc853596c797555ff3080d42c71fcf Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Mon, 25 Oct 2021 13:26:44 -0700
Subject: [PATCH] adapt testbench linux to use reset_ext

---
 wally-pipelined/regression/linux-wave.do     |  3 ++-
 wally-pipelined/testbench/testbench-linux.sv | 22 +++++++++++++-------
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index d9a631d0..30c2b036 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -2,6 +2,7 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
 add wave -noupdate /testbench/dut/hart/SATP_REGW
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
@@ -509,7 +510,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
 add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
 add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {197 ns} 0}
+WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index e5fc8574..72adf589 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -48,8 +48,8 @@ module testbench();
   ///////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////// HARDWARE ///////////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
-  logic clk, reset; 
-  initial begin reset <= 1; # 22; reset <= 0; end
+  logic clk, reset, reset_ext; 
+  initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
 
   logic [`AHBW-1:0] HRDATAEXT;
@@ -69,7 +69,7 @@ module testbench();
   logic             UARTSout;
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;
-  wallypipelinedsoc dut(.clk, .reset, 
+  wallypipelinedsoc dut(.clk, .reset_ext, .reset,
                         .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
                         .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
                         .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
@@ -219,7 +219,9 @@ module testbench();
     initial begin \
       if (CHECKPOINT!=0) begin \
         force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
-        #23; \
+        while (reset!==1) #1; \
+        while (reset!==0) #1; \
+        #1; \
         release `SIGNAL; \
       end \
     end
@@ -232,7 +234,9 @@ module testbench();
       initial begin \
         if (CHECKPOINT!=0) begin \
           force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
-          #23; \
+          while (reset!==1) #1; \
+          while (reset!==0) #1; \
+          #1; \
           release `SIGNAL_BASE[i].`SIGNAL; \
         end \
       end \
@@ -245,7 +249,9 @@ module testbench();
     initial begin \
       if (CHECKPOINT!=0) begin \
         force `SIGNAL = init``SIGNAL[0]; \
-        #23; \
+        while (reset!==1) #1; \
+        while (reset!==0) #1; \
+        #1; \
         release `SIGNAL; \
       end \
     end
@@ -302,7 +308,9 @@ module testbench();
       force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
       force `INSTRET = CHECKPOINT;
       force `CURR_PRIV = initPriv;
-      #23;
+      while (reset!==1) #1;
+      while (reset!==0) #1;
+      #1;
       release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
       release {`STATUS_FS,`STATUS_MPP};
       release {`STATUS_SPP,`STATUS_MPIE};