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More trap/csr simplification

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This commit is contained in:
David Harris 2022-05-12 22:04:20 +00:00
parent 16b86c199c
commit 662fffa830
3 changed files with 6 additions and 6 deletions
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5
pipelined/src/privileged/csr.sv
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@ -41,7 +41,7 @@ module csr #(parameter
input logic StallE, StallM, StallW,
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM,
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD,
@ -98,6 +98,7 @@ module csr #(parameter
logic [`XLEN-1:0] CSRReadVal2M;
logic [11:0] MIP_REGW_writeable;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM;
logic MTrapM, STrapM;
logic InstrValidNotFlushedM;
@ -181,6 +182,8 @@ module csr #(parameter
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
assign CSRUWriteM = CSRWriteM;
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
///////////////////////////////////////////
// CSRs

5
pipelined/src/privileged/privileged.sv
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@ -93,7 +93,6 @@ module privileged (
logic InstrAccessFaultM;
logic IllegalInstrFaultM;
logic MTrapM, STrapM;
(* mark_debug = "true" *) logic InterruptM;
logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;
@ -125,7 +124,7 @@ module privileged (
.FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .IEUAdrM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD,
@ -162,7 +161,7 @@ module privileged (
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.STATUS_MIE, .STATUS_SIE,
.InstrValidM, .CommittedM,
.TrapM, .MTrapM, .STrapM, .RetM,
.TrapM, .RetM,
.InterruptM, .IntPendingM,
.CauseM);
endmodule

2
pipelined/src/privileged/trap.sv
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@ -75,8 +75,6 @@ module trap (
BreakpointFaultM | EcallFaultM |
LoadAccessFaultM | StoreAmoAccessFaultM;
assign TrapM = ExceptionM | InterruptM;
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
assign RetM = mretM | sretM;
///////////////////////////////////////////