From 662fffa830f5de3e3861b4773fc29d1ae93079a3 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 May 2022 22:04:20 +0000
Subject: [PATCH] More trap/csr simplification

---
 pipelined/src/privileged/csr.sv        | 5 ++++-
 pipelined/src/privileged/privileged.sv | 5 ++---
 pipelined/src/privileged/trap.sv       | 2 --
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index c6eec211..18ecd01d 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -41,7 +41,7 @@ module csr #(parameter
   input  logic             StallE, StallM, StallW,
   input  logic [31:0]      InstrM, 
   input  logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM,
-  input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
+  input  logic             CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM,
   input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,
   input  logic [63:0]      MTIME_CLINT, 
   input  logic             InstrValidM, FRegWriteM, LoadStallD,
@@ -98,6 +98,7 @@ module csr #(parameter
   logic [`XLEN-1:0] CSRReadVal2M;
   logic [11:0] MIP_REGW_writeable;
   logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM;
+  logic MTrapM, STrapM;
 
   
   logic InstrValidNotFlushedM;
@@ -181,6 +182,8 @@ module csr #(parameter
   assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
   assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
   assign CSRUWriteM = CSRWriteM;  
+  assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
+  assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
 
   ///////////////////////////////////////////
   // CSRs
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 61241b17..de2ce351 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -93,7 +93,6 @@ module privileged (
   logic InstrAccessFaultM;
   logic IllegalInstrFaultM;
 
-  logic MTrapM, STrapM;
   (* mark_debug = "true" *)  logic InterruptM; 
 
   logic       STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;
@@ -125,7 +124,7 @@ module privileged (
           .FlushE, .FlushM, .FlushW,
           .StallE, .StallM, .StallW,
           .InstrM, .PCM, .SrcAM, .IEUAdrM,
-          .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
+          .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM,
           .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
           .MTIME_CLINT, 
           .InstrValidM, .FRegWriteM, .LoadStallD,
@@ -162,7 +161,7 @@ module privileged (
             .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
             .STATUS_MIE, .STATUS_SIE,
             .InstrValidM, .CommittedM,  
-            .TrapM, .MTrapM, .STrapM, .RetM,
+            .TrapM, .RetM,
             .InterruptM, .IntPendingM,
             .CauseM);
 endmodule
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index 47fdb977..4467ab6a 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -75,8 +75,6 @@ module trap (
                       BreakpointFaultM | EcallFaultM |
                       LoadAccessFaultM | StoreAmoAccessFaultM;
   assign TrapM = ExceptionM | InterruptM; 
-  assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
-  assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
   assign RetM = mretM | sretM;
 
   ///////////////////////////////////////////