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Changed to . notation for instantiation, cleaned up dmem

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This commit is contained in:
David Harris 2021-01-18 20:16:53 -05:00
parent 46d02d3818
commit 6595c7827f
21 changed files with 235 additions and 325 deletions
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1
wally-pipelined/.#modelsim.ini
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@ -1 +0,0 @@
harris@Tera.Eng.HMC.Edu.6921:1604012407

65
wally-pipelined/src/clint.sv
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@ -28,22 +28,20 @@
module clint #(parameter XLEN=32) ( module clint #(parameter XLEN=32) (
input logic clk, reset, input logic clk, reset,
input logic [1:0] MemRWM, input logic [1:0] MemRWclintM,
input logic [7:0] ByteMaskM,
input logic [15:0] AdrM, input logic [15:0] AdrM,
input logic [XLEN-1:0] WdM, input logic [XLEN-1:0] MaskedWriteDataM,
output logic [XLEN-1:0] RdM, output logic [XLEN-1:0] RdCLINTM,
output logic TimerIntM, SwIntM); output logic TimerIntM, SwIntM);
logic [63:0] MTIMECMP, MTIME; logic [63:0] MTIMECMP, MTIME;
logic MSIP; logic MSIP;
logic [XLEN-1:0] read, write;
logic [15:0] entry; logic [15:0] entry;
logic memread, memwrite; logic memread, memwrite;
assign memread = MemRWM[1]; assign memread = MemRWclintM[1];
assign memwrite = MemRWM[0]; assign memwrite = MemRWclintM[0];
// word aligned reads // word aligned reads
generate generate
@ -59,20 +57,11 @@ module clint #(parameter XLEN=32) (
if (XLEN==64) begin if (XLEN==64) begin
always_comb begin always_comb begin
case(entry) case(entry)
16'h0000: read = {63'b0, MSIP}; 16'h0000: RdCLINTM = {63'b0, MSIP};
16'h4000: read = MTIMECMP; 16'h4000: RdCLINTM = MTIMECMP;
16'hBFF8: read = MTIME; 16'hBFF8: RdCLINTM = MTIME;
default: read = 0; default: RdCLINTM = 0;
endcase endcase
write=read;
if (ByteMaskM[0]) write[7:0] = WdM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24];
if (ByteMaskM[4]) write[39:32] = WdM[39:32];
if (ByteMaskM[5]) write[47:40] = WdM[47:40];
if (ByteMaskM[6]) write[55:48] = WdM[55:48];
if (ByteMaskM[7]) write[63:56] = WdM[63:56];
end end
always_ff @(posedge clk or posedge reset) always_ff @(posedge clk or posedge reset)
if (reset) begin if (reset) begin
@ -80,27 +69,22 @@ module clint #(parameter XLEN=32) (
MTIME <= 0; MTIME <= 0;
// MTIMECMP is not reset // MTIMECMP is not reset
end else begin end else begin
if (entry == 16'h0000) MSIP <= write[0]; if (entry == 16'h0000) MSIP <= MaskedWriteDataM[0];
if (entry == 16'h4000) MTIMECMP <= write; if (entry == 16'h4000) MTIMECMP <= MaskedWriteDataM;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
if (entry == 16'hBFF8) MTIME <= write; if (entry == 16'hBFF8) MTIME <= MaskedWriteDataM;
else MTIME <= MTIME + 1; else MTIME <= MTIME + 1;
end end
end else begin // 32-bit end else begin // 32-bit
always_comb begin always_comb begin
case(entry) case(entry)
16'h0000: read = {31'b0, MSIP}; 16'h0000: RdCLINTM = {31'b0, MSIP};
16'h4000: read = MTIMECMP[31:0]; 16'h4000: RdCLINTM = MTIMECMP[31:0];
16'h4004: read = MTIMECMP[63:32]; 16'h4004: RdCLINTM = MTIMECMP[63:32];
16'hBFF8: read = MTIME[31:0]; 16'hBFF8: RdCLINTM = MTIME[31:0];
16'hBFFC: read = MTIME[63:32]; 16'hBFFC: RdCLINTM = MTIME[63:32];
default: read = 0; default: RdCLINTM = 0;
endcase endcase
write=read;
if (ByteMaskM[0]) write[7:0] = WdM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24];
end end
always_ff @(posedge clk or posedge reset) always_ff @(posedge clk or posedge reset)
if (reset) begin if (reset) begin
@ -108,20 +92,17 @@ module clint #(parameter XLEN=32) (
MTIME <= 0; MTIME <= 0;
// MTIMECMP is not reset // MTIMECMP is not reset
end else begin end else begin
if (entry == 16'h0000) MSIP <= write[0]; if (entry == 16'h0000) MSIP <= MaskedWriteDataM[0];
if (entry == 16'h4000) MTIMECMP[31:0] <= write; if (entry == 16'h4000) MTIMECMP[31:0] <= MaskedWriteDataM;
if (entry == 16'h4004) MTIMECMP[63:32] <= write; if (entry == 16'h4004) MTIMECMP[63:32] <= MaskedWriteDataM;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
if (entry == 16'hBFF8) MTIME[31:0] <= write; if (entry == 16'hBFF8) MTIME[31:0] <= MaskedWriteDataM;
else if (entry == 16'hBFFC) MTIME[63:32]<= write; else if (entry == 16'hBFFC) MTIME[63:32]<= MaskedWriteDataM;
else MTIME <= MTIME + 1; else MTIME <= MTIME + 1;
end end
end end
endgenerate endgenerate
// read
assign RdM = memread ? read: 0;
// Software interrupt when MSIP is set // Software interrupt when MSIP is set
assign SwIntM = MSIP; assign SwIntM = MSIP;
// Timer interrupt when MTIME >= MTIMECMP // Timer interrupt when MTIME >= MTIMECMP

2
wally-pipelined/src/controller.sv
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@ -75,7 +75,7 @@ module controller(
logic InstrValidE, InstrValidM; logic InstrValidE, InstrValidM;
logic PrivilegedD, PrivilegedE; logic PrivilegedD, PrivilegedE;
logic InstrAccessFaultD, InstrAccessFaultE; logic InstrAccessFaultD, InstrAccessFaultE;
logic IllegalInstrFaultD, IllegalInstrMergedD, IllegalInstrFaultE; logic IllegalInstrFaultD, IllegalInstrFaultE;
logic [18:0] ControlsD; logic [18:0] ControlsD;
logic PreIllegalInstrFaultD; logic PreIllegalInstrFaultD;
logic aluc3D; logic aluc3D;

11
wally-pipelined/src/csr.sv
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@ -95,6 +95,16 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) (
assign CSRSWriteM = CSRWriteM && (PrivilegeModeW[0]); assign CSRSWriteM = CSRWriteM && (PrivilegeModeW[0]);
assign CSRUWriteM = CSRWriteM; assign CSRUWriteM = CSRWriteM;
csri #(XLEN, MISA) csri(.*);
csrsr #(XLEN, MISA) csrsr(.*);
csrc #(XLEN, ZCOUNTERS) counters(.*);
csrm #(XLEN, MISA) csrm(.*); // Machine Mode CSRs
csrs #(XLEN, MISA) csrs(.*);
csrn #(XLEN, MISA) csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers
csru #(XLEN, MISA) csru(.*); // Floating Point Flags are part of User MOde
/*
csri #(XLEN, MISA) csri( csri #(XLEN, MISA) csri(
clk, reset, CSRMWriteM, CSRSWriteM, CSRAdrM, ExtIntM, TimerIntM, SwIntM, clk, reset, CSRMWriteM, CSRSWriteM, CSRAdrM, ExtIntM, TimerIntM, SwIntM,
MIDELEG_REGW, MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, CSRWriteValM); MIDELEG_REGW, MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, CSRWriteValM);
@ -146,6 +156,7 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) (
clk, reset, CSRUWriteM, CSRAdrM, clk, reset, CSRUWriteM, CSRAdrM,
CSRWriteValM, CSRUReadValM, SetFflagsM, FRM_REGW, IllegalCSRUAccessM CSRWriteValM, CSRUReadValM, SetFflagsM, FRM_REGW, IllegalCSRUAccessM
); );
*/
// merge CSR Reads // merge CSR Reads
assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;

50
wally-pipelined/src/csrn.sv
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@ -36,22 +36,20 @@ module csrn #(parameter XLEN=64, MISA=0,
UTVAL = 12'h043, UTVAL = 12'h043,
UIP = 12'h044) ( UIP = 12'h044) (
input logic clk, reset, input logic clk, reset,
input logic CSRUWriteM, UTrapM, input logic CSRNWriteM, UTrapM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [XLEN-1:0] resetExceptionVector, input logic [XLEN-1:0] resetExceptionVector,
input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
input logic [XLEN-1:0] CSRWriteValM, input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] CSRUReadValM, UEPC_REGW, UTVEC_REGW, output logic [XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW,
input logic [11:0] UIP_REGW, UIE_REGW, input logic [11:0] UIP_REGW, UIE_REGW,
output logic WriteUIPM, WriteUIEM, output logic WriteUIPM, WriteUIEM,
output logic WriteUSTATUSM, output logic WriteUSTATUSM,
output logic IllegalCSRUAccessM output logic IllegalCSRNAccessM
); );
logic [XLEN-1:0] zero = 0; logic [XLEN-1:0] zero = 0;
// *** add floating point CSRs here. Maybe move stuff below to csrn to support reading
// User mode CSRs below only needed when user mode traps are supported // User mode CSRs below only needed when user mode traps are supported
generate generate
if (`N_SUPPORTED) begin if (`N_SUPPORTED) begin
@ -62,13 +60,13 @@ module csrn #(parameter XLEN=64, MISA=0,
logic [XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; logic [XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
// Write enables // Write enables
assign WriteUSTATUSM = CSRUWriteM && (CSRAdrM == USTATUS); assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS);
assign WriteUTVECM = CSRUWriteM && (CSRAdrM == UTVEC); assign WriteUTVECM = CSRNWriteM && (CSRAdrM == UTVEC);
assign WriteUIPM = CSRUWriteM && (CSRAdrM == UIP); assign WriteUIPM = CSRNWriteM && (CSRAdrM == UIP);
assign WriteUIEM = CSRUWriteM && (CSRAdrM == UIE); assign WriteUIEM = CSRNWriteM && (CSRAdrM == UIE);
assign WriteUEPCM = UTrapM | (CSRUWriteM && (CSRAdrM == UEPC)); assign WriteUEPCM = UTrapM | (CSRNWriteM && (CSRAdrM == UEPC));
assign WriteUCAUSEM = UTrapM | (CSRUWriteM && (CSRAdrM == UCAUSE)); assign WriteUCAUSEM = UTrapM | (CSRNWriteM && (CSRAdrM == UCAUSE));
assign WriteUTVALM = UTrapM | (CSRUWriteM && (CSRAdrM == UTVAL)); assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL));
// CSRs // CSRs
flopenl #(XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW); flopenl #(XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW);
@ -81,28 +79,30 @@ module csrn #(parameter XLEN=64, MISA=0,
// CSR Reads // CSR Reads
always_comb begin always_comb begin
IllegalCSRUAccessM = 0; IllegalCSRNAccessM = 0;
case (CSRAdrM) case (CSRAdrM)
USTATUS: CSRUReadValM = USTATUS_REGW; USTATUS: CSRNReadValM = USTATUS_REGW;
UTVEC: CSRUReadValM = UTVEC_REGW; UTVEC: CSRNReadValM = UTVEC_REGW;
UIP: CSRUReadValM = {{(XLEN-12){1'b0}}, UIP_REGW}; UIP: CSRNReadValM = {{(XLEN-12){1'b0}}, UIP_REGW};
UIE: CSRUReadValM = {{(XLEN-12){1'b0}}, UIE_REGW}; UIE: CSRNReadValM = {{(XLEN-12){1'b0}}, UIE_REGW};
USCRATCH: CSRUReadValM = USCRATCH_REGW; USCRATCH: CSRNReadValM = USCRATCH_REGW;
UEPC: CSRUReadValM = UEPC_REGW; UEPC: CSRNReadValM = UEPC_REGW;
UCAUSE: CSRUReadValM = UCAUSE_REGW; UCAUSE: CSRNReadValM = UCAUSE_REGW;
UTVAL: CSRUReadValM = UTVAL_REGW; UTVAL: CSRNReadValM = UTVAL_REGW;
default: begin default: begin
CSRUReadValM = 0; CSRNReadValM = 0;
IllegalCSRUAccessM = 1; IllegalCSRNAccessM = 1;
end end
endcase endcase
end end
end else begin // if not supported end else begin // if not supported
assign WriteUSTATUSM = 0; assign WriteUSTATUSM = 0;
assign CSRUReadValM = 0; assign WriteUIPM = 0;
assign WriteUIEM = 0;
assign CSRNReadValM = 0;
assign UEPC_REGW = 0; assign UEPC_REGW = 0;
assign UTVEC_REGW = 0; assign UTVEC_REGW = 0;
assign IllegalCSRUAccessM = 1; assign IllegalCSRNAccessM = 1;
end end
endgenerate endgenerate
endmodule endmodule

7
wally-pipelined/src/csrs.sv
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@ -71,6 +71,8 @@ module csrs #(parameter XLEN=64, MISA=0,
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC);
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG); assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG); assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
assign WriteSIEM = CSRSWriteM && (CSRAdrM == SIE);
assign WriteSIPM = CSRSWriteM && (CSRAdrM == SIP);
assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH); assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH);
assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)); assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC));
assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)); assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE));
@ -117,9 +119,14 @@ module csrs #(parameter XLEN=64, MISA=0,
end end
end else begin end else begin
assign WriteSSTATUSM = 0; assign WriteSSTATUSM = 0;
assign WriteSIPM = 0;
assign WriteSIEM = 0;
assign CSRSReadValM = 0; assign CSRSReadValM = 0;
assign SEPC_REGW = 0; assign SEPC_REGW = 0;
assign STVEC_REGW = 0; assign STVEC_REGW = 0;
assign SEDELEG_REGW = 0;
assign SIDELEG_REGW = 0;
assign SCOUNTEREN_REGW = 0;
assign IllegalCSRSAccessM = 1; assign IllegalCSRSAccessM = 1;
end end
endgenerate endgenerate

4
wally-pipelined/src/csrsr.sv
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@ -34,11 +34,11 @@ module csrsr #(parameter XLEN=64, MISA = 0)(
input logic [XLEN-1:0] CSRWriteValM, input logic [XLEN-1:0] CSRWriteValM,
output logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, output logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STAUTS_TSR, output logic STATUS_SPP, STATUS_TSR,
output logic STATUS_MIE, STATUS_SIE output logic STATUS_MIE, STATUS_SIE
); );
logic STATUS_SD, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_SUM_INT, STATUS_MPRV, STATUS_MPRV_INT; logic STATUS_SD, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_SUM_INT, STATUS_MPRV, STATUS_MPRV_INT;
logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS, STATUS_FS_INT, STATUS_MPP_NEXT; logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS, STATUS_FS_INT, STATUS_MPP_NEXT;
logic STATUS_MPIE, STATUS_SPIE, STATUS_UPIE, STATUS_UIE; logic STATUS_MPIE, STATUS_SPIE, STATUS_UPIE, STATUS_UIE;

42
wally-pipelined/src/datapath.sv
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@ -32,9 +32,9 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
output logic [XLEN-1:0] PCF, output logic [XLEN-1:0] PCF,
input logic [31:0] InstrF, input logic [31:0] InstrF,
// Decode stage signals // Decode stage signals
output logic [6:0] opD, output logic [6:0] OpD,
output logic [2:0] funct3D, output logic [2:0] Funct3D,
output logic funct7b5D, output logic Funct7b5D,
input logic StallD, FlushD, input logic StallD, FlushD,
input logic [2:0] ImmSrcD, input logic [2:0] ImmSrcD,
input logic LoadStallD, // for performance counter input logic LoadStallD, // for performance counter
@ -55,7 +55,7 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
output logic InstrMisalignedFaultM, output logic InstrMisalignedFaultM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
output logic [XLEN-1:0] WriteDataExtM, ALUResultM, output logic [XLEN-1:0] WriteDataM, ALUResultM,
input logic [XLEN-1:0] ReadDataM, input logic [XLEN-1:0] ReadDataM,
output logic [7:0] ByteMaskM, output logic [7:0] ByteMaskM,
output logic RetM, TrapM, output logic RetM, TrapM,
@ -88,13 +88,13 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
logic [XLEN-1:0] PreSrcAE, SrcAE, SrcBE; logic [XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
logic [XLEN-1:0] ALUResultE; logic [XLEN-1:0] ALUResultE;
logic [XLEN-1:0] WriteDataE; logic [XLEN-1:0] WriteDataE;
logic [XLEN-1:0] TargetBaseE, PCTargetE; logic [XLEN-1:0] TargetBaseE;
// Memory stage signals // Memory stage signals
logic [31:0] InstrM; logic [31:0] InstrM;
logic [XLEN-1:0] PCM; logic [XLEN-1:0] PCM;
logic [XLEN-1:0] SrcAM; logic [XLEN-1:0] SrcAM;
logic [XLEN-1:0] ReadDataExtM; logic [XLEN-1:0] ReadDataExtM;
logic [XLEN-1:0] WriteDataM; logic [XLEN-1:0] WriteDataFullM;
logic [XLEN-1:0] CSRReadValM; logic [XLEN-1:0] CSRReadValM;
logic [XLEN-1:0] PrivilegedNextPCM; logic [XLEN-1:0] PrivilegedNextPCM;
logic LoadMisalignedFaultM, LoadAccessFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM;
@ -110,25 +110,23 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
logic [31:0] nop = 32'h00000013; // instruction for NOP logic [31:0] nop = 32'h00000013; // instruction for NOP
// Fetch stage pipeline register and logic; also Ex stage for branches // Fetch stage pipeline register and logic; also Ex stage for branches
pclogic #(XLEN, MISA) pclogic(clk, reset, StallF, PCSrcE, pclogic #(XLEN, MISA) pclogic(.*);
InstrF, ExtImmE, TargetBaseE, RetM, TrapM, PrivilegedNextPCM, PCF, PCPlus2or4F,
InstrMisalignedFaultM, InstrMisalignedAdrM);
// Decode stage pipeline register and logic // Decode stage pipeline register and logic
flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD); flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD);
flopenrc #(XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); flopenrc #(XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
flopenrc #(XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D); flopenrc #(XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D);
instrDecompress #(XLEN, MISA) decomp(InstrD, InstrDecompD, IllegalCompInstrD); instrDecompress #(XLEN, MISA) decomp(.*);
assign opD = InstrDecompD[6:0]; assign OpD = InstrDecompD[6:0];
assign funct3D = InstrDecompD[14:12]; assign Funct3D = InstrDecompD[14:12];
assign funct7b5D = InstrDecompD[30]; assign Funct7b5D = InstrDecompD[30];
assign Rs1D = InstrDecompD[19:15]; assign Rs1D = InstrDecompD[19:15];
assign Rs2D = InstrDecompD[24:20]; assign Rs2D = InstrDecompD[24:20];
assign RdD = InstrDecompD[11:7]; assign RdD = InstrDecompD[11:7];
regfile #(XLEN) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D); regfile #(XLEN) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D);
extend #(XLEN) ext(InstrDecompD[31:7], ImmSrcD, ExtImmD); extend #(XLEN) ext(.InstrDecompD(InstrDecompD[31:7]), .*);
// Execute stage pipeline register and logic // Execute stage pipeline register and logic
floprc #(XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E); floprc #(XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E);
@ -150,25 +148,15 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
// Memory stage pipeline register // Memory stage pipeline register
floprc #(XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM); floprc #(XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
floprc #(XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM); floprc #(XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
floprc #(XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataM); floprc #(XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM);
floprc #(XLEN) PCMReg(clk, reset, FlushM, PCE, PCM); floprc #(XLEN) PCMReg(clk, reset, FlushM, PCE, PCM);
flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM); flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM);
floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM); floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM);
memdp #(XLEN) memdp( memdp #(XLEN) memdp(.AdrM(ALUResultM), .*);
MemRWM, ReadDataM, ALUResultM, Funct3M, ReadDataExtM, WriteDataM, WriteDataExtM, ByteMaskM,
DataAccessFaultM, LoadMisalignedFaultM, LoadAccessFaultM, StoreMisalignedFaultM, StoreAccessFaultM);
// Priveleged block operates in M and W stages, handling CSRs and exceptions // Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged #(XLEN, MISA, ZCSR, ZCOUNTERS) priv( privileged #(XLEN, MISA, ZCSR, ZCOUNTERS) priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*);
clk, reset, CSRWriteM, SrcAM, InstrM, PCM,
CSRReadValM, PrivilegedNextPCM, RetM, TrapM,
InstrValidW, FloatRegWriteW, LoadStallD, PrivilegedM,
InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
LoadMisalignedFaultM, LoadAccessFaultM, StoreMisalignedFaultM, StoreAccessFaultM,
TimerIntM, ExtIntM, SwIntM,
InstrMisalignedAdrM, ALUResultM,
SetFflagsM, FRM_REGW);
// Writeback stage pipeline register and logic // Writeback stage pipeline register and logic
floprc #(XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW); floprc #(XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);

52
wally-pipelined/src/dmem.sv
View File

@ -31,36 +31,64 @@ module dmem #(parameter XLEN=32) (
input logic clk, reset, input logic clk, reset,
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [7:0] ByteMaskM, input logic [7:0] ByteMaskM,
input logic [XLEN-1:0] AdrM, WdM, input logic [XLEN-1:0] AdrM, WriteDataM,
output logic [XLEN-1:0] RdM, output logic [XLEN-1:0] ReadDataM,
output logic AccessFaultM, output logic DataAccessFaultM,
output logic TimerIntM, SwIntM, output logic TimerIntM, SwIntM,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn); output logic [31:0] GPIOPinsOut, GPIOPinsEn);
logic [XLEN-1:0] MaskedWriteDataM;
logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM; logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM;
logic TimEnM, CLINTEnM, GPIOEnM; logic TimEnM, CLINTEnM, GPIOEnM;
logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM;
// Address decoding // Address decoding
// *** need to check top bits assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF *** check top bits too
assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF *** check top bits too
assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF
assign MemRWdtimM = MemRWM & {2{TimEnM}};
assign MemRWclintM = MemRWM & {2{CLINTEnM}};
assign MemRWgpioM = MemRWM & {2{GPIOEnM}};
// tightly integrated memory // tightly integrated memory
dtim #(XLEN) dtim(clk, MemRWM & {2{TimEnM}}, ByteMaskM, AdrM[18:0], WdM, RdTimM); dtim #(XLEN) dtim(.AdrM(AdrM[18:0]), .*);
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
clint #(XLEN) clint(clk, reset, MemRWM & {2{CLINTEnM}}, ByteMaskM, AdrM[15:0], WdM, RdCLINTM, clint #(XLEN) clint(.AdrM(AdrM[15:0]), .*);
TimerIntM, SwIntM); gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*);
gpio #(XLEN) gpio(clk, reset, MemRWM & {2{GPIOEnM}}, ByteMaskM, AdrM[7:0], WdM, RdGPIOM,
GPIOPinsIn, GPIOPinsOut, GPIOPinsEn);
// *** add cache and interface to external memory & other peripherals // *** add cache and interface to external memory & other peripherals
// merge reads // merge reads
assign RdM = RdTimM | RdCLINTM | RdGPIOM; assign ReadDataM = ({XLEN{TimEnM}} & RdTimM) | ({XLEN{CLINTEnM}} & RdCLINTM) | ({XLEN{GPIOEnM}} & RdGPIOM);
assign AccessFaultM = ~(|TimEnM | CLINTEnM | GPIOEnM); assign DataAccessFaultM = ~(|TimEnM | CLINTEnM | GPIOEnM);
// byte masking
// write each byte based on the byte mask
generate
if (XLEN==64) begin
always_comb begin
MaskedWriteDataM=ReadDataM;
if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0];
if (ByteMaskM[1]) MaskedWriteDataM[15:8] = WriteDataM[15:8];
if (ByteMaskM[2]) MaskedWriteDataM[23:16] = WriteDataM[23:16];
if (ByteMaskM[3]) MaskedWriteDataM[31:24] = WriteDataM[31:24];
if (ByteMaskM[4]) MaskedWriteDataM[39:32] = WriteDataM[39:32];
if (ByteMaskM[5]) MaskedWriteDataM[47:40] = WriteDataM[47:40];
if (ByteMaskM[6]) MaskedWriteDataM[55:48] = WriteDataM[55:48];
if (ByteMaskM[7]) MaskedWriteDataM[63:56] = WriteDataM[63:56];
end
end else begin // 32-bit
always_comb begin
if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0];
if (ByteMaskM[1]) MaskedWriteDataM[15:8] = WriteDataM[15:8];
if (ByteMaskM[2]) MaskedWriteDataM[23:16] = WriteDataM[23:16];
if (ByteMaskM[3]) MaskedWriteDataM[31:24] = WriteDataM[31:24];
end
end
endgenerate
endmodule endmodule

47
wally-pipelined/src/dtim.sv
View File

@ -27,20 +27,19 @@
module dtim #(parameter XLEN=32) ( module dtim #(parameter XLEN=32) (
input logic clk, input logic clk,
input logic [1:0] MemRWM, input logic [1:0] MemRWdtimM,
input logic [7:0] ByteMaskM, input logic [7:0] ByteMaskM,
input logic [18:0] AdrM, input logic [18:0] AdrM,
// input logic [XLEN-1:0] AdrM, input logic [XLEN-1:0] WriteDataM,
input logic [XLEN-1:0] WdM, output logic [XLEN-1:0] RdTimM);
output logic [XLEN-1:0] RdM);
logic [XLEN-1:0] RAM[0:65535]; logic [XLEN-1:0] RAM[0:65535];
logic [XLEN-1:0] read, write; logic [XLEN-1:0] write;
logic [15:0] entry; logic [15:0] entry;
logic memread, memwrite; logic memread, memwrite;
assign memread = MemRWM[1]; assign memread = MemRWdtimM[1];
assign memwrite = MemRWM[0]; assign memwrite = MemRWdtimM[0];
// word aligned reads // word aligned reads
generate generate
@ -49,33 +48,35 @@ module dtim #(parameter XLEN=32) (
else else
assign #2 entry = AdrM[17:2]; assign #2 entry = AdrM[17:2];
endgenerate endgenerate
assign read = RAM[entry]; assign RdTimM = RAM[entry];
assign RdM = memread ? read: 0;
// write each byte based on the byte mask // write each byte based on the byte mask
// UInstantiate a byte-writable memory here if possible
// and drop tihs masking logic. Otherwise, use the masking
// from dmem
generate generate
if (XLEN==64) begin if (XLEN==64) begin
always_comb begin always_comb begin
write=read; write=RdTimM;
if (ByteMaskM[0]) write[7:0] = WdM[7:0]; if (ByteMaskM[0]) write[7:0] = WriteDataM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8]; if (ByteMaskM[1]) write[15:8] = WriteDataM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16]; if (ByteMaskM[2]) write[23:16] = WriteDataM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24]; if (ByteMaskM[3]) write[31:24] = WriteDataM[31:24];
if (ByteMaskM[4]) write[39:32] = WdM[39:32]; if (ByteMaskM[4]) write[39:32] = WriteDataM[39:32];
if (ByteMaskM[5]) write[47:40] = WdM[47:40]; if (ByteMaskM[5]) write[47:40] = WriteDataM[47:40];
if (ByteMaskM[6]) write[55:48] = WdM[55:48]; if (ByteMaskM[6]) write[55:48] = WriteDataM[55:48];
if (ByteMaskM[7]) write[63:56] = WdM[63:56]; if (ByteMaskM[7]) write[63:56] = WriteDataM[63:56];
end end
always_ff @(posedge clk) always_ff @(posedge clk)
if (memwrite) RAM[AdrM[18:3]] <= write; if (memwrite) RAM[AdrM[18:3]] <= write;
end else begin // 32-bit end else begin // 32-bit
always_comb begin always_comb begin
write=read; write=RdTimM;
if (ByteMaskM[0]) write[7:0] = WdM[7:0]; if (ByteMaskM[0]) write[7:0] = WriteDataM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8]; if (ByteMaskM[1]) write[15:8] = WriteDataM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16]; if (ByteMaskM[2]) write[23:16] = WriteDataM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24]; if (ByteMaskM[3]) write[31:24] = WriteDataM[31:24];
end end
always_ff @(posedge clk) always_ff @(posedge clk)
if (memwrite) RAM[AdrM[17:2]] <= write; if (memwrite) RAM[AdrM[17:2]] <= write;

20
wally-pipelined/src/extend.sv
View File

@ -26,24 +26,24 @@
`include "wally-macros.sv" `include "wally-macros.sv"
module extend #(parameter XLEN=32) ( module extend #(parameter XLEN=32) (
input logic [31:7] instr, input logic [31:7] InstrDecompD,
input logic [2:0] immsrc, input logic [2:0] ImmSrcD,
output logic [XLEN-1:0] immext); output logic [XLEN-1:0] ExtImmD);
always_comb always_comb
case(immsrc) case(ImmSrcD)
// I-type // I-type
3'b000: immext = {{(XLEN-12){instr[31]}}, instr[31:20]}; 3'b000: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:20]};
// S-type (stores) // S-type (stores)
3'b001: immext = {{(XLEN-12){instr[31]}}, instr[31:25], instr[11:7]}; 3'b001: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:25], InstrDecompD[11:7]};
// B-type (branches) // B-type (branches)
3'b010: immext = {{(XLEN-12){instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; 3'b010: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[7], InstrDecompD[30:25], InstrDecompD[11:8], 1'b0};
// J-type (jal) // J-type (jal)
3'b011: immext = {{(XLEN-20){instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 3'b011: ExtImmD = {{(XLEN-20){InstrDecompD[31]}}, InstrDecompD[19:12], InstrDecompD[20], InstrDecompD[30:21], 1'b0};
// U-type (lui, auipc) // U-type (lui, auipc)
3'b100: immext = {{(XLEN-31){instr[31]}}, instr[30:12], 12'b0}; 3'b100: ExtImmD = {{(XLEN-31){InstrDecompD[31]}}, InstrDecompD[30:12], 12'b0};
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
default: immext = 'bx; // undefined default: ExtImmD = 'bx; // undefined
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
endcase endcase
endmodule endmodule

64
wally-pipelined/src/gpio.sv
View File

@ -29,22 +29,21 @@
module gpio #(parameter XLEN=32) ( module gpio #(parameter XLEN=32) (
input logic clk, reset, input logic clk, reset,
input logic [1:0] MemRWM, input logic [1:0] MemRWgpioM,
input logic [7:0] ByteMaskM, input logic [7:0] ByteMaskM,
input logic [7:0] AdrM, input logic [7:0] AdrM,
input logic [XLEN-1:0] WdM, input logic [XLEN-1:0] MaskedWriteDataM,
output logic [XLEN-1:0] RdM, output logic [XLEN-1:0] RdGPIOM,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn); output logic [31:0] GPIOPinsOut, GPIOPinsEn);
logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL; logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
logic [XLEN-1:0] read, write; logic [7:0] entry;
logic [15:0] entry;
logic memread, memwrite; logic memread, memwrite;
assign memread = MemRWM[1]; assign memread = MemRWgpioM[1];
assign memwrite = MemRWM[0]; assign memwrite = MemRWgpioM[0];
// word aligned reads // word aligned reads
generate generate
@ -63,20 +62,11 @@ module gpio #(parameter XLEN=32) (
if (XLEN==64) begin if (XLEN==64) begin
always_comb begin always_comb begin
case(entry) case(entry)
8'h00: read = {INPUT_EN, INPUT_VAL}; 8'h00: RdGPIOM = {INPUT_EN, INPUT_VAL};
8'h08: read = {OUTPUT_VAL, OUTPUT_EN}; 8'h08: RdGPIOM = {OUTPUT_VAL, OUTPUT_EN};
8'h40: read = 0; // OUT_XOR reads as 0 8'h40: RdGPIOM = 0; // OUT_XOR reads as 0
default: read = 0; default: RdGPIOM = 0;
endcase endcase
write=read;
if (ByteMaskM[0]) write[7:0] = WdM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24];
if (ByteMaskM[4]) write[39:32] = WdM[39:32];
if (ByteMaskM[5]) write[47:40] = WdM[47:40];
if (ByteMaskM[6]) write[55:48] = WdM[55:48];
if (ByteMaskM[7]) write[63:56] = WdM[63:56];
end end
always_ff @(posedge clk or posedge reset) always_ff @(posedge clk or posedge reset)
if (reset) begin if (reset) begin
@ -84,25 +74,20 @@ module gpio #(parameter XLEN=32) (
OUTPUT_EN <= 0; OUTPUT_EN <= 0;
// OUTPUT_VAL <= 0; // spec indicates synchronous rset (software control) // OUTPUT_VAL <= 0; // spec indicates synchronous rset (software control)
end else begin end else begin
if (entry == 8'h00) INPUT_EN <= write[63:32]; if (entry == 8'h00) INPUT_EN <= MaskedWriteDataM[63:32];
if (entry == 8'h08) {OUTPUT_VAL, OUTPUT_EN} <= write; if (entry == 8'h08) {OUTPUT_VAL, OUTPUT_EN} <= MaskedWriteDataM;
if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ write[31:0]; // OUT_XOR if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ MaskedWriteDataM[31:0]; // OUT_XOR
end end
end else begin // 32-bit end else begin // 32-bit
always_comb begin always_comb begin
case(entry) case(entry)
8'h00: read = INPUT_VAL; 8'h00: RdGPIOM = INPUT_VAL;
8'h04: read = INPUT_EN; 8'h04: RdGPIOM = INPUT_EN;
8'h08: read = OUTPUT_EN; 8'h08: RdGPIOM = OUTPUT_EN;
8'h0C: read = OUTPUT_VAL; 8'h0C: RdGPIOM = OUTPUT_VAL;
8'h40: read = 0; // OUT_XOR reads as 0 8'h40: RdGPIOM = 0; // OUT_XOR reads as 0
default: read = 0; default: RdGPIOM = 0;
endcase endcase
write=read;
if (ByteMaskM[0]) write[7:0] = WdM[7:0];
if (ByteMaskM[1]) write[15:8] = WdM[15:8];
if (ByteMaskM[2]) write[23:16] = WdM[23:16];
if (ByteMaskM[3]) write[31:24] = WdM[31:24];
end end
always_ff @(posedge clk or posedge reset) always_ff @(posedge clk or posedge reset)
if (reset) begin if (reset) begin
@ -110,15 +95,12 @@ module gpio #(parameter XLEN=32) (
OUTPUT_EN <= 0; OUTPUT_EN <= 0;
//OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control) //OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
end else begin end else begin
if (entry == 8'h04) INPUT_EN <= write; if (entry == 8'h04) INPUT_EN <= MaskedWriteDataM;
if (entry == 8'h08) OUTPUT_EN <= write; if (entry == 8'h08) OUTPUT_EN <= MaskedWriteDataM;
if (entry == 8'h0C) OUTPUT_VAL <= write; if (entry == 8'h0C) OUTPUT_VAL <= MaskedWriteDataM;
if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ write; // OUT_XOR if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ MaskedWriteDataM; // OUT_XOR
end end
end end
endgenerate endgenerate
// read
assign RdM = memread ? read: 0;
endmodule endmodule

10
wally-pipelined/src/hazard.sv
View File

@ -31,7 +31,7 @@ module hazard(
input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM, input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
output logic [1:0] ForwardAE, ForwardBE, output logic [1:0] ForwardAE, ForwardBE,
output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW, output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
output logic loadStallD); output logic LoadStallD);
// forwarding logic // forwarding logic
always_comb begin always_comb begin
@ -54,11 +54,11 @@ module hazard(
// Exceptions: flush entire pipeline // Exceptions: flush entire pipeline
// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards // Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
assign loadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE)); assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
assign StallD = loadStallD; assign StallD = LoadStallD;
assign StallF = loadStallD | CSRWritePendingDEM; assign StallF = LoadStallD | CSRWritePendingDEM;
assign FlushD = PCSrcE | CSRWritePendingDEM | RetM | TrapM; assign FlushD = PCSrcE | CSRWritePendingDEM | RetM | TrapM;
assign FlushE = loadStallD | PCSrcE | RetM | TrapM; assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
assign FlushM = RetM | TrapM; assign FlushM = RetM | TrapM;
assign FlushW = TrapM; assign FlushW = TrapM;
endmodule endmodule

24
wally-pipelined/src/memdp.sv
View File

@ -31,8 +31,8 @@ module memdp #(parameter XLEN=32) (
input logic [XLEN-1:0] AdrM, input logic [XLEN-1:0] AdrM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
output logic [XLEN-1:0] ReadDataExtM, output logic [XLEN-1:0] ReadDataExtM,
input logic [XLEN-1:0] WriteDataM, input logic [XLEN-1:0] WriteDataFullM,
output logic [XLEN-1:0] WriteDataExtM, output logic [XLEN-1:0] WriteDataM,
output logic [7:0] ByteMaskM, output logic [7:0] ByteMaskM,
input logic DataAccessFaultM, input logic DataAccessFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM,
@ -40,7 +40,7 @@ module memdp #(parameter XLEN=32) (
logic [7:0] bytM; logic [7:0] bytM;
logic [15:0] HalfwordM; logic [15:0] HalfwordM;
logic UnalignedM, AccessFaultM; logic UnalignedM;
generate generate
if (XLEN == 64) begin if (XLEN == 64) begin
@ -109,11 +109,11 @@ module memdp #(parameter XLEN=32) (
// Handle subword writes // Handle subword writes
always_comb always_comb
case(Funct3M) case(Funct3M)
3'b000: WriteDataExtM = {8{WriteDataM[7:0]}}; // sb 3'b000: WriteDataM = {8{WriteDataFullM[7:0]}}; // sb
3'b001: WriteDataExtM = {4{WriteDataM[15:0]}}; // sh 3'b001: WriteDataM = {4{WriteDataFullM[15:0]}}; // sh
3'b010: WriteDataExtM = {2{WriteDataM[31:0]}}; // sw 3'b010: WriteDataM = {2{WriteDataFullM[31:0]}}; // sw
3'b011: WriteDataExtM = WriteDataM; // sw 3'b011: WriteDataM = WriteDataFullM; // sw
default: WriteDataExtM = 64'b0; default: WriteDataM = 64'b0;
endcase endcase
end else begin // 32-bit end else begin // 32-bit
@ -160,10 +160,10 @@ module memdp #(parameter XLEN=32) (
// Handle subword writes // Handle subword writes
always_comb always_comb
case(Funct3M) case(Funct3M)
3'b000: WriteDataExtM = {4{WriteDataM[7:0]}}; // sb 3'b000: WriteDataM = {4{WriteDataFullM[7:0]}}; // sb
3'b001: WriteDataExtM = {2{WriteDataM[15:0]}}; // sh 3'b001: WriteDataM = {2{WriteDataFullM[15:0]}}; // sh
3'b010: WriteDataExtM = WriteDataM; // sw 3'b010: WriteDataM = WriteDataFullM; // sw
default: WriteDataExtM = 32'b0; default: WriteDataM = 32'b0;
endcase endcase
end end
endgenerate endgenerate

50
wally-pipelined/src/pcadder.sv
View File

@ -1,50 +0,0 @@
///////////////////////////////////////////
// pcadder.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Determine next PC = PC+2 or PC+4
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-macros.sv"
module pcadder #(parameter XLEN=32) (
input logic [XLEN-1:0] pc,
input logic [31:0] instr,
output logic [XLEN-1:0] pcplus);
logic [1:0] op;
logic [XLEN-3:0] pcplusupper;
logic compressed;
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
assign op = instr[1:0];
assign compressed = (op != 2'b11); // is it a 16-bit compressed instruction?
assign pcplusupper = pc[XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4
always_comb
if (compressed) // add 2
if (pc[1]) pcplus = {pcplusupper, 2'b00};
else pcplus = {pc[XLEN-1:2], 2'b10};
else pcplus = {pcplusupper, pc[1:0]}; // add 4
endmodule

15
wally-pipelined/src/pclogic.sv
View File

@ -42,6 +42,8 @@ module pclogic #(parameter XLEN=64, MISA=0) (
logic [XLEN-1:0] ResetVector = {{(XLEN-32){1'b0}}, 32'h80000000}; logic [XLEN-1:0] ResetVector = {{(XLEN-32){1'b0}}, 32'h80000000};
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic StallExceptResolveBranchesF, PrivilegedChangePCM; logic StallExceptResolveBranchesF, PrivilegedChangePCM;
logic [XLEN-3:0] PCPlusUpperF;
logic CompressedF;
assign PrivilegedChangePCM = RetM | TrapM; assign PrivilegedChangePCM = RetM | TrapM;
@ -51,7 +53,18 @@ module pclogic #(parameter XLEN=64, MISA=0) (
mux3 #(XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); mux3 #(XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
assign PCNextF = {UnalignedPCNextF[XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment assign PCNextF = {UnalignedPCNextF[XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF); flopenl #(XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF);
pcadder #(XLEN) pcadd(PCF, InstrF, PCPlus2or4F);
// pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
assign CompressedF = (InstrF[1:0] != 2'b11); // is it a 16-bit compressed instruction?
assign PCPlusUpperF = PCF[XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4
always_comb
if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
else PCPlus2or4F = {PCF[XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
// Misaligned PC logic // Misaligned PC logic

39
wally-pipelined/src/privileged.sv
View File

@ -54,9 +54,8 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
// logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW; // logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW;
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
logic IllegalCSRAccess, IllegalInstrFaultM; logic IllegalCSRAccessM, IllegalInstrFaultM;
logic SwInt, TimerInt, ExtInt;
logic BreakpointFaultM, EcallFaultM; logic BreakpointFaultM, EcallFaultM;
logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM; logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM;
logic MTrapM, STrapM, UTrapM; logic MTrapM, STrapM, UTrapM;
@ -67,13 +66,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
logic [11:0] MIP_REGW, MIE_REGW; logic [11:0] MIP_REGW, MIE_REGW;
// track the current privilege level // track the current privilege level
privilegeModeReg #(XLEN, MISA) pmr (clk, reset, mretM, sretM, uretM, TrapM, privilegeModeReg #(XLEN, MISA) pmr (.*);
STATUS_MPP, STATUS_SPP, MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
CauseM, NextPrivilegeModeM, PrivilegeModeW);
// decode privileged instructions // decode privileged instructions
privilegeDecoder #(MISA) pmd(InstrM[31:20], PrivilegedM, IllegalInstrFaultInM, IllegalCSRAccess, PrivilegeModeW, STATUS_TSR, privilegeDecoder #(MISA) pmd(.InstrM(InstrM[31:20]), .*);
IllegalInstrFaultM, uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM);
// Extract exceptions by name and handle them // Extract exceptions by name and handle them
assign BreakpointFaultM = ebreakM; // could have other causes too assign BreakpointFaultM = ebreakM; // could have other causes too
@ -81,35 +77,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)(
assign InstrPageFaultM = 0; assign InstrPageFaultM = 0;
assign LoadPageFaultM = 0; assign LoadPageFaultM = 0;
assign StorePageFaultM = 0; assign StorePageFaultM = 0;
trap #(XLEN, MISA) trap(clk, reset, InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, trap #(XLEN, MISA) trap(.*);
BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
LoadPageFaultM, StorePageFaultM,
mretM, sretM, uretM, PrivilegeModeW, NextPrivilegeModeM,
MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
MIP_REGW, MIE_REGW, STATUS_MIE, STATUS_SIE,
InstrMisalignedAdrM, ALUResultM, InstrM,
TrapM, MTrapM, STrapM, UTrapM, RetM,
PrivilegedNextPCM, CauseM, NextFaultMtvalM
// MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
);
// Control and Status Registers // Control and Status Registers
csr #(XLEN, MISA, ZCSR, ZCOUNTERS) csr(clk, reset, csr #(XLEN, MISA, ZCSR, ZCOUNTERS) csr(.*);
InstrM, PCM, SrcAM,
CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
TimerIntM, ExtIntM, SwIntM,
InstrValidW, FloatRegWriteW, LoadStallD,
NextPrivilegeModeM, PrivilegeModeW,
CauseM, NextFaultMtvalM,
STATUS_MPP, STATUS_SPP, STATUS_TSR,
MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
MIP_REGW, MIE_REGW, STATUS_MIE, STATUS_SIE,
SetFflagsM, FRM_REGW,
// MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
CSRReadValM, IllegalCSRAccess
);
endmodule endmodule

1
wally-pipelined/src/testbench.sv
View File

@ -234,6 +234,7 @@ string tests32i[] = {
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
// instantiate device to be tested // instantiate device to be tested
assign GPIOPinsIn = 0;
wallypipelined #(XLEN, MISA, ZCSR, ZCOUNTERS) dut( wallypipelined #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(
clk, reset, WriteData, DataAdr, MemRW, clk, reset, WriteData, DataAdr, MemRW,
GPIOPinsIn, GPIOPinsOut, GPIOPinsEn GPIOPinsIn, GPIOPinsOut, GPIOPinsEn

9
wally-pipelined/src/wallypipelined.sv
View File

@ -68,11 +68,8 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
logic ExtIntM = 0; // not yet connected logic ExtIntM = 0; // not yet connected
// instantiate processor and memories // instantiate processor and memories
wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) hart( wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) hart(.ALUResultM(DataAdrM), .*);
clk, reset, PCF, InstrF, MemRWM, ByteMaskM, DataAdrM,
WriteDataM, ReadDataM, TimerIntM, ExtIntM, SwIntM, InstrAccessFaultF, DataAccessFaultM);
imem #(XLEN) imem(PCF, InstrF, InstrAccessFaultF); imem #(XLEN) imem(.AdrF(PCF), .*);
dmem #(XLEN) dmem(clk, reset, MemRWM, ByteMaskM, DataAdrM, WriteDataM, ReadDataM, dmem #(XLEN) dmem(.AdrM(DataAdrM), .*);
DataAccessFaultM, TimerIntM, SwIntM, GPIOPinsIn, GPIOPinsOut, GPIOPinsEn);
endmodule endmodule

33
wally-pipelined/src/wallypipelinedhart.sv
View File

@ -37,9 +37,9 @@ module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1)
input logic InstrAccessFaultF, input logic InstrAccessFaultF,
input logic DataAccessFaultM); input logic DataAccessFaultM);
logic [6:0] opD; logic [2:0] Funct3D;
logic [2:0] funct3D; logic Funct7b5D;
logic funct7b5D; logic [6:0] OpD;
logic [2:0] ImmSrcD; logic [2:0] ImmSrcD;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [2:0] FlagsE; logic [2:0] FlagsE;
@ -61,7 +61,7 @@ module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1)
logic [1:0] ForwardAE, ForwardBE; logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, FlushD, FlushE, FlushM, FlushW; logic StallF, StallD, FlushD, FlushE, FlushM, FlushW;
logic PrivilegedChangePCM, TrapM; logic RetM, TrapM;
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW; logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
logic TargetSrcE; logic TargetSrcE;
@ -69,32 +69,13 @@ module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1)
logic [2:0] FRM_REGW; logic [2:0] FRM_REGW;
logic FloatRegWriteW; logic FloatRegWriteW;
controller c(clk, reset, controller c(.*);
opD, funct3D, funct7b5D, ImmSrcD, datapath #(XLEN, MISA, ZCSR, ZCOUNTERS) dp(.*);
StallD, FlushD, IllegalCompInstrD, hazard hz(.*);
FlushE, FlagsE, PCSrcE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, MemReadE,
FlushM, MemRWM, CSRWriteM, PrivilegedM, IllegalInstrFaultM, Funct3M, RegWriteM,
FlushW, RegWriteW, ResultSrcW, InstrValidW, CSRWritePendingDEM,
InstrAccessFaultF, InstrAccessFaultM);
datapath #(XLEN, MISA, ZCSR, ZCOUNTERS)
dp(clk, reset,
StallF, PCF, InstrF,
opD, funct3D, funct7b5D, StallD, FlushD, ImmSrcD, LoadStallD, IllegalCompInstrD,
FlushE, ForwardAE, ForwardBE, PCSrcE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, FlagsE,
FlushM, MemRWM, CSRWriteM, PrivilegedM, InstrAccessFaultM, IllegalInstrFaultM,
TimerIntM, ExtIntM, SwIntM, InstrMisalignedFaultM,
Funct3M, WriteDataM, ALUResultM, ReadDataM, ByteMaskM, PrivilegedChangePCM, TrapM,
SetFflagsM, DataAccessFaultM,
FlushW, RegWriteW, ResultSrcW, InstrValidW, FloatRegWriteW, FRM_REGW,
Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW);
// add FPU here, with SetFflagsM, FRM_REGW // add FPU here, with SetFflagsM, FRM_REGW
// presently stub out SetFlagsM and FloatRegWriteW // presently stub out SetFlagsM and FloatRegWriteW
assign SetFflagsM = 0; assign SetFflagsM = 0;
assign FloatRegWriteW = 0; assign FloatRegWriteW = 0;
hazard hz(Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
PCSrcE, MemReadE, RegWriteM, RegWriteW, CSRWritePendingDEM, PrivilegedChangePCM, TrapM,
ForwardAE, ForwardBE, StallF, StallD, FlushD, FlushE, FlushM, FlushW, LoadStallD);
endmodule endmodule

2
wally-pipelined/wally-pipelined.do
View File

@ -60,7 +60,7 @@ add wave -divider
add wave /testbench/InstrMName add wave /testbench/InstrMName
add wave /testbench/dut/dmem/dtim/memwrite add wave /testbench/dut/dmem/dtim/memwrite
add wave -hex /testbench/dut/dmem/AdrM add wave -hex /testbench/dut/dmem/AdrM
add wave -hex /testbench/dut/dmem/WdM add wave -hex /testbench/dut/dmem/WriteDataM
add wave -divider add wave -divider
add wave -hex /testbench/dut/hart/dp/PCW add wave -hex /testbench/dut/hart/dp/PCW
#add wave -hex /testbench/dut/hart/dp/InstrW #add wave -hex /testbench/dut/hart/dp/InstrW