forked from Github_Repos/cvw
95 lines
4.1 KiB
Systemverilog
95 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// dmem.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Data memory
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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// *** need idiom to map onto cache RAM with byte writes
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// *** and use memread signal to reduce power when reads aren't needed
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module dmem #(parameter XLEN=32) (
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input logic clk, reset,
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input logic [1:0] MemRWM,
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input logic [7:0] ByteMaskM,
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input logic [XLEN-1:0] AdrM, WriteDataM,
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output logic [XLEN-1:0] ReadDataM,
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output logic DataAccessFaultM,
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output logic TimerIntM, SwIntM,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn);
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logic [XLEN-1:0] MaskedWriteDataM;
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logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM;
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logic TimEnM, CLINTEnM, GPIOEnM;
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logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM;
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// Address decoding
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assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF *** check top bits too
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assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
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assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF
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assign MemRWdtimM = MemRWM & {2{TimEnM}};
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assign MemRWclintM = MemRWM & {2{CLINTEnM}};
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assign MemRWgpioM = MemRWM & {2{GPIOEnM}};
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// tightly integrated memory
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dtim #(XLEN) dtim(.AdrM(AdrM[18:0]), .*);
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// memory-mapped I/O peripherals
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clint #(XLEN) clint(.AdrM(AdrM[15:0]), .*);
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gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*);
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// *** add cache and interface to external memory & other peripherals
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// merge reads
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assign ReadDataM = ({XLEN{TimEnM}} & RdTimM) | ({XLEN{CLINTEnM}} & RdCLINTM) | ({XLEN{GPIOEnM}} & RdGPIOM);
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assign DataAccessFaultM = ~(|TimEnM | CLINTEnM | GPIOEnM);
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// byte masking
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// write each byte based on the byte mask
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generate
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if (XLEN==64) begin
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always_comb begin
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MaskedWriteDataM=ReadDataM;
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if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0];
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if (ByteMaskM[1]) MaskedWriteDataM[15:8] = WriteDataM[15:8];
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if (ByteMaskM[2]) MaskedWriteDataM[23:16] = WriteDataM[23:16];
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if (ByteMaskM[3]) MaskedWriteDataM[31:24] = WriteDataM[31:24];
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if (ByteMaskM[4]) MaskedWriteDataM[39:32] = WriteDataM[39:32];
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if (ByteMaskM[5]) MaskedWriteDataM[47:40] = WriteDataM[47:40];
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if (ByteMaskM[6]) MaskedWriteDataM[55:48] = WriteDataM[55:48];
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if (ByteMaskM[7]) MaskedWriteDataM[63:56] = WriteDataM[63:56];
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end
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end else begin // 32-bit
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always_comb begin
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if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0];
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if (ByteMaskM[1]) MaskedWriteDataM[15:8] = WriteDataM[15:8];
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if (ByteMaskM[2]) MaskedWriteDataM[23:16] = WriteDataM[23:16];
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if (ByteMaskM[3]) MaskedWriteDataM[31:24] = WriteDataM[31:24];
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end
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end
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endgenerate
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endmodule
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