From 63a824cca17fcc508b99eafbbd69e8fe4a255a67 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 30 Aug 2022 15:27:19 -0500 Subject: [PATCH] More progress. --- pipelined/regression/wave.do | 34 ++++++++++++++++++-- pipelined/src/cache/AHBBuscachefsm.sv | 2 +- pipelined/src/ebu/ahbmultimanager.sv | 46 +++++++++++++++++++++++++-- pipelined/src/lsu/lsu.sv | 11 +++++-- 4 files changed, 84 insertions(+), 9 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index d76eb8b2..7c4a31ca 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -169,11 +169,33 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE +add wave -noupdate -expand -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/BusState add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel +add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive +add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURSTD +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/HRDATA +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHREADY +add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn @@ -196,11 +218,16 @@ add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/BusCurrState add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/RW add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/CacheRW add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/Cacheable add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HRDATA +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/cachedp/WordCount add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid @@ -305,6 +332,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine @@ -513,8 +541,8 @@ add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRA add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {2306 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 2} {27610 ns} 0} {{Cursor 3} {334914 ns} 1} {{Cursor 4} {335206 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -529,4 +557,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2137 ns} {2477 ns} +WaveRestoreZoom {27292 ns} {27764 ns} diff --git a/pipelined/src/cache/AHBBuscachefsm.sv b/pipelined/src/cache/AHBBuscachefsm.sv index c468c020..46165875 100644 --- a/pipelined/src/cache/AHBBuscachefsm.sv +++ b/pipelined/src/cache/AHBBuscachefsm.sv @@ -131,7 +131,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold, assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) | (BusCurrState == STATE_CAPTURE & ~HREADY) | (BusCurrState == STATE_CACHE_ACCESS & ~HREADY & |WordCount) ? AHB_NONSEQ : - (BusCurrState == STATE_CACHE_ACCESS) ? AHB_SEQ : AHB_IDLE; + (BusCurrState == STATE_CACHE_ACCESS & |WordCount) ? AHB_SEQ : AHB_IDLE; assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0] (BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]); diff --git a/pipelined/src/ebu/ahbmultimanager.sv b/pipelined/src/ebu/ahbmultimanager.sv index 3c3881f6..d58459df 100644 --- a/pipelined/src/ebu/ahbmultimanager.sv +++ b/pipelined/src/ebu/ahbmultimanager.sv @@ -93,7 +93,13 @@ module ahbmultimanager logic IFUReq, LSUReq; logic IFUActive, LSUActive; - + + logic WordCntEn; + logic [4-1:0] NextWordCount, WordCount, WordCountDelayed; + logic WordCountFlag; + logic [2:0] LocalBurstType; + logic CntReset; + logic [3:0] Threshold; assign HCLK = clk; assign HRESETn = ~reset; @@ -149,7 +155,7 @@ module ahbmultimanager assign save[1] = 1'b0; assign restore[1] = 1'b0; assign dis[1] = 1'b0; - assign sel[1] = NextBusState == ARBITRATE ? LSUReq : 1'b0; + assign sel[1] = NextBusState == ARBITRATE ? 1'b1: LSUReq; @@ -163,7 +169,7 @@ module ahbmultimanager case (BusState) IDLE: if (both) NextBusState = ARBITRATE; else NextBusState = IDLE; - ARBITRATE: if (HREADY)NextBusState = IDLE; + ARBITRATE: if (HREADY & WordCountFlag) NextBusState = IDLE; else NextBusState = ARBITRATE; default: NextBusState = IDLE; endcase // case (BusState) @@ -173,5 +179,39 @@ module ahbmultimanager assign HWDATA = LSUHWDATA; assign HWSTRB = LSUHWSTRB; + flopenr #(4) + WordCountReg(.clk(HCLK), + .reset(~HRESETn | CntReset), + .en(WordCntEn), + .d(NextWordCount), + .q(WordCount)); + + // Used to store data from data phase of AHB. + flopenr #(4) + WordCountDelayedReg(.clk(HCLK), + .reset(~HRESETn | CntReset), + .en(WordCntEn), + .d(WordCount), + .q(WordCountDelayed)); + assign NextWordCount = WordCount + 1'b1; + + assign CntReset = NextBusState == IDLE; + assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access. + assign WordCntEn = (NextBusState == ARBITRATE & HREADY); + + logic [2:0] HBURSTD; + + flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD)); + + always_comb begin + case(HBURSTD) + 0: Threshold = 4'b0000; + 3: Threshold = 4'b0011; // INCR4 + 5: Threshold = 4'b0111; // INCR8 + 7: Threshold = 4'b1111; // INCR16 + default: Threshold = 4'b0000; // INCR without end. + endcase + end + endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index eed9df5e..60f5c3a7 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -246,6 +246,8 @@ module lsu ( logic [LOGBWPL-1:0] WordCount; logic SelUncachedAdr, DCacheBusAck; logic SelBusWord; + logic [`XLEN-1:0] LSUHWDATA_noDELAY; //*** change name + logic [`XLEN/8-1:0] ByteMaskMDelay; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -268,10 +270,15 @@ module lsu ( .SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .Cacheable(CacheableM), .BusStall, .BusCommitted(BusCommittedM)); - mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), + mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), - .s(SelUncachedAdr), .y(LSUHWDATA)); + .s(SelUncachedAdr), .y(LSUHWDATA_noDELAY)); + + flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM[`XLEN/8-1:0], LSUHWSTRB); + + end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; assign LSUHADDR = LSUPAdrM;