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Renamed modules in privileged unit

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This commit is contained in:
David Harris 2021-01-28 23:21:12 -05:00
parent fd2f854a69
commit 618c6e4813
5 changed files with 44 additions and 82 deletions
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2
wally-pipelined/lint-wally
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@ -1,7 +1,7 @@
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
verilator --lint-only -Iconfig/rv64ic src/*.sv
verilator --lint-only --top-module wallypipelined -Iconfig/rv64ic src/*.sv
# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include wally-config.vh are found

4
wally-pipelined/src/privilegeDecoder.sv → wally-pipelined/src/privdec.sv
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// privilegeDecoder.sv
// privdec.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
@ -26,7 +26,7 @@
`include "wally-config.vh"
module privilegeDecoder (
module privdec (
input logic [31:20] InstrM,
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM,
input logic [1:0] PrivilegeModeW,

59
wally-pipelined/src/privilegeModeReg.sv
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@ -1,59 +0,0 @@
///////////////////////////////////////////
// privilegeModeReg.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Track current privilege mode
// See RISC-V Privileged Mode Specification 20190608
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module privilegeModeReg (
input logic clk, reset,
input logic mretM, sretM, uretM, TrapM,
input logic [1:0] STATUS_MPP,
input logic STATUS_SPP,
input logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM,
output logic [1:0] NextPrivilegeModeM, PrivilegeModeW);
logic md, sd;
// get bits of DELEG registers based on CAUSE
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
always_comb
if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
else if (mretM) NextPrivilegeModeM = STATUS_MPP;
else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
else if (uretM) NextPrivilegeModeM = `U_MODE;
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (PrivilegeModeW == `U_MODE)
if (`N_SUPPORTED & `U_SUPPORTED & md & sd) NextPrivilegeModeM = `U_MODE;
else if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
else if (PrivilegeModeW == `S_MODE)
if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
else NextPrivilegeModeM = `M_MODE;
end else NextPrivilegeModeM = PrivilegeModeW; // stay at same level when there is no exception or return
flop #(2) PrivlegeReg(clk, NextPrivilegeModeM, PrivilegeModeW);
endmodule

48
wally-pipelined/src/privileged.sv
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@ -68,23 +68,56 @@ module privileged (
logic STATUS_SPP, STATUS_TSR;
logic STATUS_MIE, STATUS_SIE;
logic [11:0] MIP_REGW, MIE_REGW;
logic md, sd;
///////////////////////////////////////////
// track the current privilege level
privilegeModeReg pmr(.*);
///////////////////////////////////////////
// decode privileged instructions
privilegeDecoder pmd(.InstrM(InstrM[31:20]), .*);
// get bits of DELEG registers based on CAUSE
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
// PrivilegeMode FSM
always_comb
if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
else if (mretM) NextPrivilegeModeM = STATUS_MPP;
else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
else if (uretM) NextPrivilegeModeM = `U_MODE;
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (PrivilegeModeW == `U_MODE)
if (`N_SUPPORTED & `U_SUPPORTED & md & sd) NextPrivilegeModeM = `U_MODE;
else if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
else if (PrivilegeModeW == `S_MODE)
if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
else NextPrivilegeModeM = `M_MODE;
end else NextPrivilegeModeM = PrivilegeModeW;
flop #(2) privmodereg(clk, NextPrivilegeModeM, PrivilegeModeW);
///////////////////////////////////////////
// decode privileged instructions
///////////////////////////////////////////
privdec pmd(.InstrM(InstrM[31:20]), .*);
///////////////////////////////////////////
// Control and Status Registers
///////////////////////////////////////////
csr csr(.*);
///////////////////////////////////////////
// Extract exceptions by name and handle them
///////////////////////////////////////////
assign BreakpointFaultM = ebreakM; // could have other causes too
assign EcallFaultM = ecallM;
assign InstrPageFaultM = 0;
assign LoadPageFaultM = 0;
assign StorePageFaultM = 0;
trap trap(.*);
// Control and Status Registers
csr csr(.*);
// pipeline fault signals
flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
@ -95,6 +128,7 @@ module privileged (
{IllegalIEUInstrFaultE, InstrAccessFaultE},
{IllegalIEUInstrFaultM, InstrAccessFaultM});
trap trap(.*);
endmodule

13
wally-pipelined/wally.old
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@ -1,13 +0,0 @@
// riscvfullpipelined.sv
`include "wally-macros.sv"