forked from Github_Repos/cvw
Renamed modules in privileged unit
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@ -1,7 +1,7 @@
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# check for warnings in Verilog code
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# check for warnings in Verilog code
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# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
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# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
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verilator --lint-only -Iconfig/rv64ic src/*.sv
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verilator --lint-only --top-module wallypipelined -Iconfig/rv64ic src/*.sv
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# --lint-only just runs lint rather than trying to compile and simulate
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# --lint-only just runs lint rather than trying to compile and simulate
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# -I points to the include directory where files such as `include wally-config.vh are found
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# -I points to the include directory where files such as `include wally-config.vh are found
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// privilegeDecoder.sv
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// privdec.sv
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//
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// Modified:
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@ -26,7 +26,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module privilegeDecoder (
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module privdec (
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input logic [31:20] InstrM,
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input logic [31:20] InstrM,
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input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM,
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input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM,
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] PrivilegeModeW,
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@ -1,59 +0,0 @@
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///////////////////////////////////////////
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// privilegeModeReg.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Track current privilege mode
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// See RISC-V Privileged Mode Specification 20190608
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module privilegeModeReg (
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input logic clk, reset,
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input logic mretM, sretM, uretM, TrapM,
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input logic [1:0] STATUS_MPP,
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input logic STATUS_SPP,
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input logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM,
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output logic [1:0] NextPrivilegeModeM, PrivilegeModeW);
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logic md, sd;
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// get bits of DELEG registers based on CAUSE
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assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
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assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
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always_comb
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if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
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else if (mretM) NextPrivilegeModeM = STATUS_MPP;
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else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else if (uretM) NextPrivilegeModeM = `U_MODE;
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else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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if (PrivilegeModeW == `U_MODE)
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if (`N_SUPPORTED & `U_SUPPORTED & md & sd) NextPrivilegeModeM = `U_MODE;
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else if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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else if (PrivilegeModeW == `S_MODE)
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if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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else NextPrivilegeModeM = `M_MODE;
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end else NextPrivilegeModeM = PrivilegeModeW; // stay at same level when there is no exception or return
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flop #(2) PrivlegeReg(clk, NextPrivilegeModeM, PrivilegeModeW);
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endmodule
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@ -68,23 +68,56 @@ module privileged (
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logic STATUS_SPP, STATUS_TSR;
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logic STATUS_SPP, STATUS_TSR;
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logic STATUS_MIE, STATUS_SIE;
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logic STATUS_MIE, STATUS_SIE;
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logic [11:0] MIP_REGW, MIE_REGW;
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logic [11:0] MIP_REGW, MIE_REGW;
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logic md, sd;
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///////////////////////////////////////////
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// track the current privilege level
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// track the current privilege level
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privilegeModeReg pmr(.*);
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///////////////////////////////////////////
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// decode privileged instructions
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// get bits of DELEG registers based on CAUSE
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privilegeDecoder pmd(.InstrM(InstrM[31:20]), .*);
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assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
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assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
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// PrivilegeMode FSM
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always_comb
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if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
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else if (mretM) NextPrivilegeModeM = STATUS_MPP;
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else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else if (uretM) NextPrivilegeModeM = `U_MODE;
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else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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if (PrivilegeModeW == `U_MODE)
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if (`N_SUPPORTED & `U_SUPPORTED & md & sd) NextPrivilegeModeM = `U_MODE;
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else if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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else if (PrivilegeModeW == `S_MODE)
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if (`S_SUPPORTED & md) NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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else NextPrivilegeModeM = `M_MODE;
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end else NextPrivilegeModeM = PrivilegeModeW;
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flop #(2) privmodereg(clk, NextPrivilegeModeM, PrivilegeModeW);
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///////////////////////////////////////////
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// decode privileged instructions
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///////////////////////////////////////////
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privdec pmd(.InstrM(InstrM[31:20]), .*);
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///////////////////////////////////////////
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// Control and Status Registers
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///////////////////////////////////////////
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csr csr(.*);
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///////////////////////////////////////////
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// Extract exceptions by name and handle them
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// Extract exceptions by name and handle them
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///////////////////////////////////////////
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assign BreakpointFaultM = ebreakM; // could have other causes too
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assign BreakpointFaultM = ebreakM; // could have other causes too
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assign EcallFaultM = ecallM;
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assign EcallFaultM = ecallM;
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assign InstrPageFaultM = 0;
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assign InstrPageFaultM = 0;
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assign LoadPageFaultM = 0;
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assign LoadPageFaultM = 0;
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assign StorePageFaultM = 0;
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assign StorePageFaultM = 0;
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trap trap(.*);
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// Control and Status Registers
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csr csr(.*);
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// pipeline fault signals
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// pipeline fault signals
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flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
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flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
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@ -95,6 +128,7 @@ module privileged (
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{IllegalIEUInstrFaultE, InstrAccessFaultE},
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{IllegalIEUInstrFaultE, InstrAccessFaultE},
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{IllegalIEUInstrFaultM, InstrAccessFaultM});
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{IllegalIEUInstrFaultM, InstrAccessFaultM});
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trap trap(.*);
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endmodule
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endmodule
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@ -1,13 +0,0 @@
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// riscvfullpipelined.sv
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`include "wally-macros.sv"
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