From 6031269de88c21f271f997d7a72e0a6b856c3733 Mon Sep 17 00:00:00 2001
From: Teo Ene <teodor@rivendell.ecen.okstate.edu>
Date: Wed, 3 Mar 2021 18:17:53 -0600
Subject: [PATCH] Implemented fix disucssed with Elizabeth

---
 wally-pipelined/regression/wally-coremark.do  | 20 +++++++++----------
 .../testbench/testbench-coremark.sv           |  3 +++
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
index 056b34cb..f3205ae5 100644
--- a/wally-pipelined/regression/wally-coremark.do
+++ b/wally-pipelined/regression/wally-coremark.do
@@ -52,23 +52,23 @@ add wave -divider
 #add wave /testbench/dut/hart/FlushM
 #add wave /testbench/dut/hart/FlushW
 
-add wave -divider
+add wave -divider Fetch
 add wave -hex /testbench/dut/hart/ifu/PCF
 add wave -hex /testbench/dut/hart/ifu/InstrF
 add wave /testbench/InstrFName
-add wave -divider
+add wave -divider Decode
 add wave -hex /testbench/dut/hart/ifu/PCD
 add wave -hex /testbench/dut/hart/ifu/InstrD
 add wave /testbench/InstrDName
-add wave -divider
+add wave -divider Execute
 add wave -hex /testbench/dut/hart/ifu/PCE
 add wave -hex /testbench/dut/hart/ifu/InstrE
 add wave /testbench/InstrEName
-add wave -divider
+add wave -divider Memory
 add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
-add wave -divider
+add wave -divider Write
 add wave -hex /testbench/dut/hart/ifu/PCW
 add wave -hex /testbench/dut/hart/ifu/InstrW
 add wave /testbench/InstrWName
@@ -76,7 +76,7 @@ add wave /testbench/InstrWName
 #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
 #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
 #add wave /testbench/dut/hart/ieu/dp/PCSrcE
-add wave -divider
+add wave -divider Regfile
 #add wave /testbench/dut/uncore/dtim/memwrite
 #add wave -hex /testbench/dut/uncore/HADDR
 #add wave -hex /testbench/dut/uncore/HWDATA
@@ -88,9 +88,9 @@ add wave -divider
 #add wave -hex /testbench/dut/hart/ieu/dp/RdW
 #add wave -hex -r /testbench/*
 add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
+add wave -divider Misc
 add wave -divider
-add wave -divider
-add wave -hex -r /testbench/dut/hart/ebu/ReadDataW
+#add wave -hex -r /testbench/dut/uncore/dtim/RAM
 
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
@@ -106,6 +106,6 @@ configure wave -childrowmargin 2
 set DefaultRadix hexadecimal
 
 -- Run the Simulation 
-run 3000
-#run -all
+#run 3000
+run -all
 #quit
diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv
index 9f458567..a8d53715 100644
--- a/wally-pipelined/testbench/testbench-coremark.sv
+++ b/wally-pipelined/testbench/testbench-coremark.sv
@@ -66,6 +66,7 @@ module testbench();
                 dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
   // initialize tests
+  integer j;
   initial
     begin
       totalerrors = 0;
@@ -73,6 +74,8 @@ module testbench();
       memfilename = tests[0];
       $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
+      for(j=1911; j < 65535; j = j+1)
+        dut.uncore.dtim.RAM[j] = 64'b0;
       reset = 1; # 22; reset = 0;
     end
   // generate clock to sequence tests