From a0a4b09c94ae4fbaee37b3da4661b1aa598e7bc5 Mon Sep 17 00:00:00 2001 From: Abe Date: Fri, 18 Jun 2021 11:46:25 -0400 Subject: [PATCH 1/5] Updated directory coremark_bare's wally-config file to define PMP_ENTRIES --- wally-pipelined/config/coremark_bare/wally-config.vh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 5b62a23e..828dd084 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -52,6 +52,9 @@ `define ITLB_ENTRY_BITS 5 `define DTLB_ENTRY_BITS 5 +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 16 + // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -101,7 +104,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" +`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE"//comments From 03a45aeef197e946e23c6e673f15c551816fb967 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 11:58:16 -0400 Subject: [PATCH 2/5] restore graphical buildroot sim --- wally-pipelined/testbench/testbench-linux.sv | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 9f80a33d..f9d2415e 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -474,18 +474,18 @@ module testbench(); end string PCtextD,PCtextE,PCtextM,PCtext2; - always_ff @(posedge clk, posedge reset) - if (reset) begin - PCtextE <= #1 "(reset)"; - PCtextM <= #1 "(reset)"; - end else begin - if (~dut.hart.StallE) - if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; - else PCtextE <= #1 PCtextD; - if (~dut.hart.StallM) - if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; - else PCtextM <= #1 PCtextE; - end + //always_ff @(posedge clk, posedge reset) + // if (reset) begin + // PCtextE <= #1 "(reset)"; + // PCtextM <= #1 "(reset)"; + // end else begin + // if (~dut.hart.StallE) + // if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; + // else PCtextE <= #1 PCtextD; + // if (~dut.hart.StallM) + // if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; + // else PCtextM <= #1 PCtextE; + // end initial begin From 33312caeb1f66d67c3158730fccf788d14851997 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 12:36:25 -0400 Subject: [PATCH 3/5] Restored wally-busybear testbench now that graphical sim is working --- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-linux.sv | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 0be7fcdd..11876dde 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -#do ./wave-dos/linux-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index f9d2415e..b3552cb1 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -498,10 +498,8 @@ module testbench(); always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin if(~HWRITE) begin #2; - $display("test point"); if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin if (dut.hart.ifu.PCD !== lastPCD) begin - $display("tp2"); lastCheckInstrD = CheckInstrD; lastPC <= dut.hart.ifu.PCD; lastPC2 <= lastPC; @@ -528,22 +526,16 @@ module testbench(); end end else begin - $display("tp4"); if($feof(data_file_PC)) begin $display("no more PC data to read"); `ERROR end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; - $display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); while (PCtext2 != "***") begin - $display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); PCtextD = {PCtextD, " ", PCtext2}; - $display("tp8"); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); - $display("tp9"); end - $display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); if(dut.hart.ifu.PCD === pcExpected) begin if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs From 16266d978a41ad01dc41b6e4666acc754e363cec Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Jun 2021 12:02:59 -0500 Subject: [PATCH 4/5] Icache now uses physical lenght bits rather than XLEN. --- wally-pipelined/src/cache/ICacheCntrl.sv | 14 +++++++------- wally-pipelined/src/cache/ICacheMem.sv | 10 +++++----- wally-pipelined/src/cache/icache.sv | 6 +++--- wally-pipelined/src/ifu/ifu.sv | 4 +++- 4 files changed, 18 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index d8383965..9037748c 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Signals to/from cache memory // The read coming out of it input logic [31:0] ICacheMemReadData, input logic ICacheMemReadValid, // The address at which we want to search the cache memory - output logic [`XLEN-1:0] PCTagF, - output logic [`XLEN-1:0] PCNextIndexF, + output logic [`PA_BITS-1:0] PCTagF, + output logic [`PA_BITS-1:0] PCNextIndexF, output logic ICacheReadEn, // Load data into the cache output logic ICacheMemWriteEnable, @@ -133,8 +133,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF; - logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPFinalF, PCSpillF; + logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; logic [31:0] FinalInstrRawF; @@ -174,7 +174,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( assign PCNextIndexF = PCPFinalF; // truncate the offset from PCPF for memory address generation - assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH]; + assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; // Detect if the instruction is compressed assign CompressedF = FinalInstrRawF[1:0] != 2'b11; diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index 4ea3d22a..9a5fdbe2 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) // If flush is high, invalidate the entire cache input logic flush, - input logic [`XLEN-1:0] PCTagF, // physical address - input logic [`XLEN-1:0] PCNextIndexF, // virtual address + input logic [`PA_BITS-1:0] PCTagF, // physical address + input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address input logic WriteEnable, input logic [BLOCKLEN-1:0] WriteLine, output logic [BLOCKLEN-1:0] ReadLineF, @@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) localparam OFFSETLEN = $clog2(BLOCKBYTELEN); localparam INDEXLEN = $clog2(NUMLINES); // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48 - localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; + localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; logic [TAGLEN-1:0] LookupTag; logic [NUMLINES-1:0] ValidOut; @@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) cachetags (.*, .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .ReadData(LookupTag), - .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) + .WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]) ); // Correctly handle the valid bits @@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) end DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; end - assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); + assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]); endmodule diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index e3a0829b..907d30fa 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -31,8 +31,8 @@ module icache input logic clk, reset, input logic StallF, StallD, input logic FlushD, - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Data read in from the ebu unit input logic [`XLEN-1:0] InstrInF, input logic InstrAckF, @@ -58,7 +58,7 @@ module icache logic ICacheMemWriteEnable; logic [BLOCKLEN-1:0] ICacheMemWriteData; logic EndFetchState; - logic [`XLEN-1:0] PCTagF, PCNextIndexF; + logic [`PA_BITS-1:0] PCTagF, PCNextIndexF; // Output signals from cache memory logic [31:0] ICacheMemReadData; logic ICacheMemReadValid; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ca0071b1..275cee76 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -138,7 +138,9 @@ module ifu ( // jarred 2021-03-14 Add instrution cache block to remove rd2 assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live - icache icache(.*); + icache icache(.*, + .PCNextF(PCNextF[`PA_BITS-1:0]), + .PCPF(PCPFmmu)); From a57c63aa7b5e958c3aff046cf706bdca57408788 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Jun 2021 12:05:02 -0500 Subject: [PATCH 5/5] Improved some names in icache. --- wally-pipelined/src/cache/ICacheCntrl.sv | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 9037748c..d73a85bc 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -133,7 +133,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`PA_BITS-1:0] PCPreFinalF, PCPFinalF, PCSpillF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; @@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. - assign PCSpillF = PCPF + `XLEN'b10; + assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width. // now we have to select between these three PCs assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary - assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; + assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF; // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // *** read enable may not be necessary. @@ -170,8 +170,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( .d(PCMux), .q(PCMux_q)); - assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF; - assign PCNextIndexF = PCPFinalF; + assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF; // truncate the offset from PCPF for memory address generation assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; @@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // more zeros after the addition. This will be the number of offset bits less the AHBByteLength. - logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; + logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}}; // verilator lint_off WIDTH