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slmnemo 2022-06-09 17:50:47 -07:00
parent 3e8d3bae88
commit 5a6eae214a
2 changed files with 6 additions and 5 deletions
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9
pipelined/src/ebu/ahblite.sv
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@ -133,8 +133,9 @@ module ahblite (
assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
assign #1 HADDR = AccessAddress; assign #1 HADDR = AccessAddress;
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway // assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; // assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; // Commented out due to not using ISize.
assign HSIZE = (`XLEN == 64) ? 3'b011 : 3'b010;
assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst.
/* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE.
@ -167,8 +168,8 @@ module ahblite (
assign IFUBusHRDATA = HRDATA; assign IFUBusHRDATA = HRDATA;
assign LSUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA;
assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY; assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);
assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY; assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE));
assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign IFUBusAck = HREADY & (BusState == INSTRREAD);
assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));

2
pipelined/src/lsu/busdp.sv
View File

@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
output logic BusStall, output logic BusStall,
output logic BusCommittedM); output logic BusCommittedM);
localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1; localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [`PA_BITS-1:0] LocalLSUBusAdr;
logic [LOGWPL-1:0] WordCountDelayed; logic [LOGWPL-1:0] WordCountDelayed;