From 5a6eae214a27576d1ba5f49f9ef88f1825f81828 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 9 Jun 2022 17:50:47 -0700 Subject: [PATCH] ? --- pipelined/src/ebu/ahblite.sv | 9 +++++---- pipelined/src/lsu/busdp.sv | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 68561cba..4b12e1a1 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -133,8 +133,9 @@ module ahblite ( assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 HADDR = AccessAddress; - assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; + // assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway + // assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; // Commented out due to not using ISize. + assign HSIZE = (`XLEN == 64) ? 3'b011 : 3'b010; assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. @@ -167,8 +168,8 @@ module ahblite ( assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD) & HREADY; - assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState == IDLE) & (NextBusState == MEMWRITE)) & HREADY; + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); + assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index f1156b44..5139efdc 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -68,7 +68,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusStall, output logic BusCommittedM); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 1; + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; logic [LOGWPL-1:0] WordCountDelayed;