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Switched coremark to RV64IM

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This commit is contained in:
Teo Ene 2021-03-17 22:39:56 -05:00
parent d2fe42d6d0
commit 57f1ca5259
2 changed files with 5 additions and 5 deletions
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4
wally-pipelined/regression/wally-coremark_bare.do
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@ -111,6 +111,6 @@ set DefaultRadix hexadecimal
-- Run the Simulation -- Run the Simulation
#run 7402000 #run 7402000
#run 12750 #run 12750
#run -all run -all
run 5000 #run 21400
#quit #quit

6
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -48,7 +48,7 @@ module testbench();
// pick tests based on modes supported // pick tests based on modes supported
initial initial
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
string signame, memfilename; string signame, memfilename;
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout; logic UARTSin, UARTSout;
@ -76,8 +76,8 @@ module testbench();
$readmemh(memfilename, dut.uncore.dtim.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=268437829; j < 268566528; j = j+1) for(j=268437829; j < 268566528; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0; dut.uncore.dtim.RAM[j] = 64'b0;
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
reset = 1; # 22; reset = 0; reset = 1; # 22; reset = 0;
end end
// generate clock to sequence tests // generate clock to sequence tests