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Found an issue where the btb was not forwarding the valid bit!

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Ross Thompson 2023-01-28 17:00:50 -06:00
parent 6d9c463893
commit 57deb68fb3
1 changed files with 4 additions and 1 deletions
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5
pipelined/src/ifu/brpred/btb.sv
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@ -56,6 +56,7 @@ module btb
logic [`XLEN-1:0] PredPCD; logic [`XLEN-1:0] PredPCD;
logic [3:0] PredInstrClassD; // *** copy of reg outside module logic [3:0] PredInstrClassD; // *** copy of reg outside module
logic UpdateEn; logic UpdateEn;
logic TablePredValidF;
// hashing function for indexing the PC // hashing function for indexing the PC
// We have Depth bits to index, but XLEN bits as the input. // We have Depth bits to index, but XLEN bits as the input.
@ -93,9 +94,11 @@ module btb
end else if ((UpdateEn) & ~StallM & ~FlushM) begin end else if ((UpdateEn) & ~StallM & ~FlushM) begin
ValidBits[PCEIndex] <= #1 |InstrClassE; ValidBits[PCEIndex] <= #1 |InstrClassE;
end end
PredValidF = ValidBits[PCNextFIndex]; TablePredValidF = ValidBits[PCNextFIndex];
end end
assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
// An optimization may be using a PC relative address. // An optimization may be using a PC relative address.