forked from Github_Repos/cvw
Moved the ReadDataW register into the datapath.
The StallW from the hazard unit controls this. Previously it was in the dcache and controlled by both the HPTW and hazard unit. This caused an issue when the CPU expected the data to stay constant while stalled, but the HPTW was causing the data to be modified.
This commit is contained in:
Ross Thompson
parent
fbbfc799b9
commit
551e3491af
@ -2,31 +2,29 @@ onerror {resume}
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quietly WaveActivateNextPane {} 0
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/test
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/PCtextM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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@ -158,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -253,61 +251,61 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
@ -317,16 +315,17 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/StallW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
@ -352,12 +351,21 @@ add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu
|
|||||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/hptw/genblk1/PRegEn
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {7778 ns} 0}
|
WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {41795656 ns} 0}
|
||||||
quietly wave cursor active 4
|
quietly wave cursor active 4
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
@ -373,4 +381,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {7636 ns} {7946 ns}
|
WaveRestoreZoom {41795482 ns} {41795818 ns}
|
||||||
|
|||||||
29
wally-pipelined/src/cache/dcache.sv
vendored
29
wally-pipelined/src/cache/dcache.sv
vendored
@ -29,7 +29,7 @@ module dcache
|
|||||||
(input logic clk,
|
(input logic clk,
|
||||||
input logic reset,
|
input logic reset,
|
||||||
input logic StallM,
|
input logic StallM,
|
||||||
input logic StallW,
|
input logic StallWtoDCache,
|
||||||
input logic FlushM,
|
input logic FlushM,
|
||||||
input logic FlushW,
|
input logic FlushW,
|
||||||
|
|
||||||
@ -43,7 +43,6 @@ module dcache
|
|||||||
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
||||||
|
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
|
||||||
output logic [`XLEN-1:0] ReadDataM,
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
output logic DCacheStall,
|
output logic DCacheStall,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
@ -194,7 +193,7 @@ module dcache
|
|||||||
|
|
||||||
flopenr #(7) Funct7WReg(.clk(clk),
|
flopenr #(7) Funct7WReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.en(~StallW),
|
.en(~StallWtoDCache),
|
||||||
.d(Funct7M),
|
.d(Funct7M),
|
||||||
.q(Funct7W));
|
.q(Funct7W));
|
||||||
|
|
||||||
@ -335,7 +334,7 @@ module dcache
|
|||||||
.HRDATAMasked(ReadDataM));
|
.HRDATAMasked(ReadDataM));
|
||||||
|
|
||||||
// This is a confusing point.
|
// This is a confusing point.
|
||||||
// The final read data should be updated only if the CPU's StallW is low
|
// The final read data should be updated only if the CPU's StallWtoDCache is low
|
||||||
// which means the CPU is ready to take data. Or if the CPU just became
|
// which means the CPU is ready to take data. Or if the CPU just became
|
||||||
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
// busy. Then when we exit CPU_BUSY we want to ensure the data is not
|
||||||
// updated, this is ~PreviousCPUBusy.
|
// updated, this is ~PreviousCPUBusy.
|
||||||
@ -345,10 +344,6 @@ module dcache
|
|||||||
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
||||||
|
|
||||||
|
|
||||||
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
|
||||||
.en(~StallW),
|
|
||||||
.d(ReadDataM),
|
|
||||||
.q(ReadDataW));
|
|
||||||
|
|
||||||
|
|
||||||
// write path
|
// write path
|
||||||
@ -488,7 +483,7 @@ module dcache
|
|||||||
NextState = STATE_AMO_UPDATE;
|
NextState = STATE_AMO_UPDATE;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
else NextState = STATE_AMO_UPDATE;
|
else NextState = STATE_AMO_UPDATE;
|
||||||
@ -500,7 +495,7 @@ module dcache
|
|||||||
DCacheAccess = 1'b1;
|
DCacheAccess = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -515,7 +510,7 @@ module dcache
|
|||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
|
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -557,7 +552,7 @@ module dcache
|
|||||||
end
|
end
|
||||||
STATE_AMO_WRITE: begin
|
STATE_AMO_WRITE: begin
|
||||||
SelAMOWrite = 1'b1;
|
SelAMOWrite = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -618,7 +613,7 @@ module dcache
|
|||||||
//SelAdrM = 1'b1;
|
//SelAdrM = 1'b1;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -637,7 +632,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_MISS_WRITE_WORD_DELAY: begin
|
STATE_MISS_WRITE_WORD_DELAY: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -774,7 +769,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -805,7 +800,7 @@ module dcache
|
|||||||
|
|
||||||
STATE_UNCACHED_WRITE_DONE: begin
|
STATE_UNCACHED_WRITE_DONE: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
@ -815,7 +810,7 @@ module dcache
|
|||||||
STATE_UNCACHED_READ_DONE: begin
|
STATE_UNCACHED_READ_DONE: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
SelUncached = 1'b1;
|
SelUncached = 1'b1;
|
||||||
if(StallW) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdrM = 1'b1;
|
SelAdrM = 1'b1;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -57,8 +57,9 @@ module datapath (
|
|||||||
input logic RegWriteW,
|
input logic RegWriteW,
|
||||||
input logic SquashSCW,
|
input logic SquashSCW,
|
||||||
input logic [2:0] ResultSrcW,
|
input logic [2:0] ResultSrcW,
|
||||||
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
// input logic [`XLEN-1:0] PCLinkW,
|
// input logic [`XLEN-1:0] PCLinkW,
|
||||||
input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW,
|
input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
|
||||||
// Hazard Unit signals
|
// Hazard Unit signals
|
||||||
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
|
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
|
||||||
output logic [4:0] RdE, RdM, RdW
|
output logic [4:0] RdE, RdM, RdW
|
||||||
@ -86,7 +87,7 @@ module datapath (
|
|||||||
logic [`XLEN-1:0] ALUResultW;
|
logic [`XLEN-1:0] ALUResultW;
|
||||||
logic [`XLEN-1:0] WriteDataW;
|
logic [`XLEN-1:0] WriteDataW;
|
||||||
logic [`XLEN-1:0] ResultW;
|
logic [`XLEN-1:0] ResultW;
|
||||||
|
|
||||||
// Decode stage
|
// Decode stage
|
||||||
assign Rs1D = InstrD[19:15];
|
assign Rs1D = InstrD[19:15];
|
||||||
assign Rs2D = InstrD[24:20];
|
assign Rs2D = InstrD[24:20];
|
||||||
@ -137,6 +138,11 @@ module datapath (
|
|||||||
assign SCResultW = 0;
|
assign SCResultW = 0;
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
||||||
|
.en(~StallW),
|
||||||
|
.d(ReadDataM),
|
||||||
|
.q(ReadDataW));
|
||||||
|
|
||||||
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
|
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
// This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage.
|
// This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage.
|
||||||
|
|||||||
@ -61,9 +61,10 @@ module ieu (
|
|||||||
input logic [`XLEN-1:0] FIntResM,
|
input logic [`XLEN-1:0] FIntResM,
|
||||||
|
|
||||||
// Writeback stage
|
// Writeback stage
|
||||||
input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW,
|
input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
|
||||||
input logic FWriteIntW,
|
input logic FWriteIntW,
|
||||||
output logic [4:0] RdW,
|
output logic [4:0] RdW,
|
||||||
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
// input logic [`XLEN-1:0] PCLinkW,
|
// input logic [`XLEN-1:0] PCLinkW,
|
||||||
output logic InstrValidM,
|
output logic InstrValidM,
|
||||||
// hazards
|
// hazards
|
||||||
|
|||||||
@ -52,7 +52,7 @@ module lsu
|
|||||||
input logic [`XLEN-1:0] MemAdrM,
|
input logic [`XLEN-1:0] MemAdrM,
|
||||||
input logic [`XLEN-1:0] MemAdrE,
|
input logic [`XLEN-1:0] MemAdrE,
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
|
|
||||||
// cpu privilege
|
// cpu privilege
|
||||||
input logic [1:0] PrivilegeModeW,
|
input logic [1:0] PrivilegeModeW,
|
||||||
@ -121,7 +121,6 @@ module lsu
|
|||||||
logic DTLBMissM;
|
logic DTLBMissM;
|
||||||
// logic [`XLEN-1:0] PTE;
|
// logic [`XLEN-1:0] PTE;
|
||||||
logic DTLBWriteM;
|
logic DTLBWriteM;
|
||||||
logic [`XLEN-1:0] HPTWReadPTE;
|
|
||||||
logic HPTWStall;
|
logic HPTWStall;
|
||||||
logic [`XLEN-1:0] HPTWPAdrE;
|
logic [`XLEN-1:0] HPTWPAdrE;
|
||||||
// logic [`XLEN-1:0] HPTWPAdrM;
|
// logic [`XLEN-1:0] HPTWPAdrM;
|
||||||
@ -164,7 +163,7 @@ module lsu
|
|||||||
.PageType,
|
.PageType,
|
||||||
.ITLBWriteF(ITLBWriteF),
|
.ITLBWriteF(ITLBWriteF),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
.DTLBWriteM(DTLBWriteM),
|
||||||
.HPTWReadPTE(HPTWReadPTE),
|
.HPTWReadPTE(ReadDataM),
|
||||||
.HPTWStall(HPTWStall),
|
.HPTWStall(HPTWStall),
|
||||||
.TranslationPAdr,
|
.TranslationPAdr,
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWRead(HPTWRead),
|
||||||
@ -193,7 +192,6 @@ module lsu
|
|||||||
.CommittedM(CommittedM),
|
.CommittedM(CommittedM),
|
||||||
.PendingInterruptM(PendingInterruptM),
|
.PendingInterruptM(PendingInterruptM),
|
||||||
.StallW(StallW),
|
.StallW(StallW),
|
||||||
.ReadDataW(ReadDataW),
|
|
||||||
.DataMisalignedM(DataMisalignedM),
|
.DataMisalignedM(DataMisalignedM),
|
||||||
.LSUStall(LSUStall),
|
.LSUStall(LSUStall),
|
||||||
// DCACHE
|
// DCACHE
|
||||||
@ -205,7 +203,6 @@ module lsu
|
|||||||
.MemAdrEtoDCache(MemAdrEtoDCache),
|
.MemAdrEtoDCache(MemAdrEtoDCache),
|
||||||
.StallWtoDCache(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||||
.ReadDataWfromDCache(ReadDataWfromDCache),
|
|
||||||
.CommittedMfromDCache(CommittedMfromDCache),
|
.CommittedMfromDCache(CommittedMfromDCache),
|
||||||
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
||||||
.DCacheStall(DCacheStall));
|
.DCacheStall(DCacheStall));
|
||||||
@ -294,7 +291,7 @@ module lsu
|
|||||||
dcache dcache(.clk(clk),
|
dcache dcache(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.StallM(StallM),
|
.StallM(StallM),
|
||||||
.StallW(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.FlushM(FlushM),
|
.FlushM(FlushM),
|
||||||
.FlushW(FlushWtoDCache),
|
.FlushW(FlushWtoDCache),
|
||||||
.MemRWM(MemRWMtoDCache),
|
.MemRWM(MemRWMtoDCache),
|
||||||
@ -305,8 +302,7 @@ module lsu
|
|||||||
.MemPAdrM(MemPAdrM),
|
.MemPAdrM(MemPAdrM),
|
||||||
.VAdr(MemAdrM[11:0]),
|
.VAdr(MemAdrM[11:0]),
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataWfromDCache),
|
.ReadDataM(ReadDataM),
|
||||||
.ReadDataM(HPTWReadPTE),
|
|
||||||
.DCacheStall(DCacheStall),
|
.DCacheStall(DCacheStall),
|
||||||
.CommittedM(CommittedMfromDCache),
|
.CommittedM(CommittedMfromDCache),
|
||||||
.DCacheMiss,
|
.DCacheMiss,
|
||||||
|
|||||||
@ -44,7 +44,6 @@ module lsuArb
|
|||||||
input logic StallW,
|
input logic StallW,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
// to CPU
|
// to CPU
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
|
||||||
output logic DataMisalignedM,
|
output logic DataMisalignedM,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
output logic LSUStall,
|
output logic LSUStall,
|
||||||
@ -63,7 +62,6 @@ module lsuArb
|
|||||||
// from D Cache
|
// from D Cache
|
||||||
input logic CommittedMfromDCache,
|
input logic CommittedMfromDCache,
|
||||||
input logic DataMisalignedMfromDCache,
|
input logic DataMisalignedMfromDCache,
|
||||||
input logic [`XLEN-1:0] ReadDataWfromDCache,
|
|
||||||
input logic DCacheStall
|
input logic DCacheStall
|
||||||
|
|
||||||
);
|
);
|
||||||
@ -95,7 +93,6 @@ module lsuArb
|
|||||||
// demux the inputs from LSU to walker or cpu's data port.
|
// demux the inputs from LSU to walker or cpu's data port.
|
||||||
|
|
||||||
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
|
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
|
||||||
assign ReadDataW = /*SelPTW ? `XLEN'b0 : */ReadDataWfromDCache; // probably can avoid this demux
|
|
||||||
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
|
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
|
||||||
// *** need to rename DcacheStall and Datastall.
|
// *** need to rename DcacheStall and Datastall.
|
||||||
// not clear at all. I think it should be LSUStall from the LSU,
|
// not clear at all. I think it should be LSUStall from the LSU,
|
||||||
|
|||||||
@ -134,7 +134,8 @@ module wallypipelinedhart
|
|||||||
// cpu lsu interface
|
// cpu lsu interface
|
||||||
logic [2:0] Funct3M;
|
logic [2:0] Funct3M;
|
||||||
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
|
logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM;
|
||||||
logic [`XLEN-1:0] ReadDataW;
|
logic [`XLEN-1:0] ReadDataM;
|
||||||
|
logic [`XLEN-1:0] ReadDataW;
|
||||||
logic CommittedM;
|
logic CommittedM;
|
||||||
|
|
||||||
// AHB ifu interface
|
// AHB ifu interface
|
||||||
@ -195,7 +196,7 @@ module wallypipelinedhart
|
|||||||
.MemAdrE(MemAdrE),
|
.MemAdrE(MemAdrE),
|
||||||
.MemAdrM(MemAdrM),
|
.MemAdrM(MemAdrM),
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataW),
|
.ReadDataM(ReadDataM),
|
||||||
|
|
||||||
// connected to ahb (all stay the same)
|
// connected to ahb (all stay the same)
|
||||||
.CommitM(CommitM),
|
.CommitM(CommitM),
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user