diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 72deeac0..9ff93020 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -27,16 +27,16 @@ module hazard( // Detect hazards - input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, - input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, - input logic LSUStall, ICacheStallF, - input logic FPUStallD, FStallD, - input logic DivBusyE,FDivBusyE, - input logic EcallFaultM, BreakpointFaultM, - input logic InvalidateICacheM, +(* mark_debug = "true" *) input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, +(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, +(* mark_debug = "true" *) input logic LSUStall, ICacheStallF, +(* mark_debug = "true" *) input logic FPUStallD, FStallD, +(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE, +(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, +(* mark_debug = "true" *) input logic InvalidateICacheM, // Stall & flush outputs - output logic StallF, StallD, StallE, StallM, StallW, - output logic FlushF, FlushD, FlushE, FlushM, FlushW +(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, +(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW ); logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; diff --git a/wally-pipelined/src/sdc/clkdivider.sv b/wally-pipelined/src/sdc/clkdivider.sv index 8dc8a312..d4218aa4 100644 --- a/wally-pipelined/src/sdc/clkdivider.sv +++ b/wally-pipelined/src/sdc/clkdivider.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // clock divider.sv // -// Written: Ross Thompson September 18, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 18, 2021 +// Converted to system verilog. // // Purpose: clock divider for sd flash // diff --git a/wally-pipelined/src/sdc/counter.sv b/wally-pipelined/src/sdc/counter.sv index 689c443e..29ef2fd1 100644 --- a/wally-pipelined/src/sdc/counter.sv +++ b/wally-pipelined/src/sdc/counter.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // counter.sv // -// Written: Ross Thompson -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson +// Converted to system verilog. // // Purpose: basic up counter // diff --git a/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv b/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv index 444555c7..9f12abc0 100644 --- a/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv +++ b/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // crc16 sipo np ce // -// Written: Ross Thompson September 18, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 18, 2021 +// Converted to system verilog. // // Purpose: CRC16 generator SIPO using register_ce // w/o appending any zero-bits to the message diff --git a/wally-pipelined/src/sdc/crc7_pipo.sv b/wally-pipelined/src/sdc/crc7_pipo.sv index 46ba0062..4172a2c9 100644 --- a/wally-pipelined/src/sdc/crc7_pipo.sv +++ b/wally-pipelined/src/sdc/crc7_pipo.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // crc7 sipo np ce // -// Written: Ross Thompson September 18, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 18, 2021 +// Converted to system verilog. // // Purpose: takes 40 bits of input, generates 7 bit CRC after a single // clock cycle! diff --git a/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv b/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv index 5721aa95..7039c1fc 100644 --- a/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv +++ b/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // crc16 sipo np ce // -// Written: Ross Thompson September 18, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 18, 2021 // // Purpose: CRC7 generator SIPO using register_ce // w/o appending any zero-bits othe message diff --git a/wally-pipelined/src/sdc/piso_generic_ce.sv b/wally-pipelined/src/sdc/piso_generic_ce.sv index ad1d6a17..022d0e8b 100644 --- a/wally-pipelined/src/sdc/piso_generic_ce.sv +++ b/wally-pipelined/src/sdc/piso_generic_ce.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // piso generic ce // -// Written: Ross Thompson September 18, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 18, 2021 // // // A component of the Wally configurable RISC-V project. diff --git a/wally-pipelined/src/sdc/sd_clk_fsm.sv b/wally-pipelined/src/sdc/sd_clk_fsm.sv index 558f695f..d56b443d 100644 --- a/wally-pipelined/src/sdc/sd_clk_fsm.sv +++ b/wally-pipelined/src/sdc/sd_clk_fsm.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // sd_clk_fsm.sv // -// Written: Ross Thompson September 19, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 19, 2021 // // Purpose: Controls clock dividers. // Replaces s_disable_sd_clocks, s_select_hs_clk, s_enable_hs_clk diff --git a/wally-pipelined/src/sdc/sd_cmd_fsm.sv b/wally-pipelined/src/sdc/sd_cmd_fsm.sv index fedb4b2f..ef9467e9 100644 --- a/wally-pipelined/src/sdc/sd_cmd_fsm.sv +++ b/wally-pipelined/src/sdc/sd_cmd_fsm.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // sd_clk_fsm.sv // -// Written: Ross Thompson September 19, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 19, 2021 // // Purpose: Finite state machine for the SD CMD bus // diff --git a/wally-pipelined/src/sdc/sd_dat_fsm.sv b/wally-pipelined/src/sdc/sd_dat_fsm.sv index 7726f1cb..72747b83 100644 --- a/wally-pipelined/src/sdc/sd_dat_fsm.sv +++ b/wally-pipelined/src/sdc/sd_dat_fsm.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // sd_dat_fsm.sv // -// Written: Ross Thompson September 19, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 19, 2021 // // Purpose: Runs in parallel with sd_cmd_fsm to control activity on the DAT // bus of the SD card. diff --git a/wally-pipelined/src/sdc/sd_top.sv b/wally-pipelined/src/sdc/sd_top.sv index b18b3d17..02315271 100644 --- a/wally-pipelined/src/sdc/sd_top.sv +++ b/wally-pipelined/src/sdc/sd_top.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // sd_top.sv // -// Written: Ross Thompson September 19, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 19, 2021 // // Purpose: SD card controller // diff --git a/wally-pipelined/src/sdc/sipo_generic_ce.sv b/wally-pipelined/src/sdc/sipo_generic_ce.sv index 210767af..e76a41b1 100644 --- a/wally-pipelined/src/sdc/sipo_generic_ce.sv +++ b/wally-pipelined/src/sdc/sipo_generic_ce.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // sipo_generic_ce // -// Written: Ross Thompson September 20, 2021 -// Modified: +// Written: Richard Davis +// Modified: Ross Thompson September 20, 2021 // // Purpose: serial to n-bit parallel shift register using register_ce. // When given a n-bit word as input transmit the message serially MSB (leftmost)