forked from Github_Repos/cvw
		
	Setup the main regression test to be able to handle coremark.
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				@ -1,6 +1,4 @@
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onerror {resume}
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quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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@ -102,7 +102,8 @@ logic [3:0] dummy;
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        "testsBP64":                      tests = testsBP64;
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        "wally64i":                       tests = wally64i; // *** redo
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        "wally64priv":                    tests = wally64priv;// *** redo
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        "imperas64periph":                  tests = imperas64periph;
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        "imperas64periph":                tests = imperas64periph;
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        "coremark":                       tests = coremark;
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      endcase 
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    end else begin // RV32
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      case (TEST)
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@ -161,7 +162,7 @@ logic [3:0] dummy;
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  // Track names of instructions
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  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
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                dut.core.ifu.FinalInstrRawF,
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                dut.core.ifu.FinalInstrRawF[31:0],
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                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
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                dut.core.ifu.InstrM,  InstrW,
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                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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@ -181,12 +182,13 @@ logic [3:0] dummy;
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      //  strings, but uses a load double to read them in.  If the last 2 bytes are
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      //  not initialized the compare results in an 'x' which propagates through 
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      // the design.
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      if (`XLEN == 32) meminit = 32'hFEDC0123;
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      else meminit = 64'hFEDCBA9876543210;
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      //if (`XLEN == 32) meminit = 32'hFEDC0123;
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      //else meminit = 64'hFEDCBA9876543210;
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      // *** broken because DTIM also drives RAM
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      if (`TESTSBP) begin
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      if (TEST == "coremark") begin
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    	for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
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    	  dut.uncore.ram.ram.RAM[i] = meminit;
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          // *** why does coremark need these extra addresses zeroed?
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    	  dut.uncore.ram.ram.RAM[i] = 64'h0;//meminit;
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    	end
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      end
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      // read test vectors into memory
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@ -27,16 +27,23 @@
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`define RISCVARCHTEST "1"
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`define WALLYTEST "2"
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`define MYIMPERASTEST   "3"
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`define COREMARK "4"
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// *** remove MYIMPERASTEST cases when ported 
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string tvpaths[] = '{
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    "../../addins/imperas-riscv-tests/work/",
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    "../../addins/riscv-arch-test/work/",
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    "../../tests/wally-riscv-arch-test/work/",
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    "../../tests/imperas-riscv-tests/work/"
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    "../../tests/imperas-riscv-tests/work/",
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    "../../benchmarks/riscv-coremark/work/"
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};
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   // *** make sure these are somewhere
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  string coremark[] = '{
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    `COREMARK,
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    "coremark.bare.riscv", "100000"
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  };
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  string imperas64a[] = '{
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    `MYIMPERASTEST,
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    "rv64a/WALLY-AMO", "2110",
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