diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index 74314896..8535c82b 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -1,6 +1,4 @@
 onerror {resume}
-quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp
-quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index cd9a2288..65a760cb 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -102,7 +102,8 @@ logic [3:0] dummy;
         "testsBP64":                      tests = testsBP64;
         "wally64i":                       tests = wally64i; // *** redo
         "wally64priv":                    tests = wally64priv;// *** redo
-        "imperas64periph":                  tests = imperas64periph;
+        "imperas64periph":                tests = imperas64periph;
+        "coremark":                       tests = coremark;
       endcase 
     end else begin // RV32
       case (TEST)
@@ -161,7 +162,7 @@ logic [3:0] dummy;
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
-                dut.core.ifu.FinalInstrRawF,
+                dut.core.ifu.FinalInstrRawF[31:0],
                 dut.core.ifu.InstrD, dut.core.ifu.InstrE,
                 dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
@@ -181,12 +182,13 @@ logic [3:0] dummy;
       //  strings, but uses a load double to read them in.  If the last 2 bytes are
       //  not initialized the compare results in an 'x' which propagates through 
       // the design.
-      if (`XLEN == 32) meminit = 32'hFEDC0123;
-      else meminit = 64'hFEDCBA9876543210;
+      //if (`XLEN == 32) meminit = 32'hFEDC0123;
+      //else meminit = 64'hFEDCBA9876543210;
       // *** broken because DTIM also drives RAM
-      if (`TESTSBP) begin
+      if (TEST == "coremark") begin
     	for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
-    	  dut.uncore.ram.ram.RAM[i] = meminit;
+          // *** why does coremark need these extra addresses zeroed?
+    	  dut.uncore.ram.ram.RAM[i] = 64'h0;//meminit;
     	end
       end
       // read test vectors into memory
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index 424f2282..14c131cf 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -26,17 +26,24 @@
 `define IMPERASTEST   "0"
 `define RISCVARCHTEST "1"
 `define WALLYTEST "2"
-`define MYIMPERASTEST   "3" 
+`define MYIMPERASTEST   "3"
+`define COREMARK "4"
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
     "../../addins/imperas-riscv-tests/work/",
     "../../addins/riscv-arch-test/work/",
     "../../tests/wally-riscv-arch-test/work/",
-    "../../tests/imperas-riscv-tests/work/"
+    "../../tests/imperas-riscv-tests/work/",
+    "../../benchmarks/riscv-coremark/work/"
 };
 
    // *** make sure these are somewhere
+  string coremark[] = '{
+    `COREMARK,
+    "coremark.bare.riscv", "100000"
+  };
+
   string imperas64a[] = '{
     `MYIMPERASTEST,
     "rv64a/WALLY-AMO", "2110",