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Clean up sqrt initialization mux

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David Harris 2022-12-30 06:55:20 -08:00
parent dba3ffe767
commit 4fb8396867
1 changed files with 12 additions and 17 deletions
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27
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -51,20 +51,14 @@ module fdivsqrtpreproc (
); );
logic [`DIVb-1:0] XPreproc; logic [`DIVb-1:0] XPreproc;
logic [`DIVb:0] SqrtX; logic [`DIVb:0] PreSqrtX;
logic [`DIVb+3:0] DivX; logic [`DIVb+3:0] DivX, SqrtX;
logic [`NE+1:0] QeE; logic [`NE+1:0] QeE;
// Intdiv signals
logic [`DIVb-1:0] IFNormLenX, IFNormLenD; logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
logic [`DIVBLEN:0] mE; logic [`DIVBLEN:0] mE, ell;
logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
logic [`LOGRK:0] pPrTrunc;
logic [`DIVb+3:0] PreShiftX; logic [`DIVb+3:0] PreShiftX;
logic NumZeroE; logic NumZeroE;
// ***can probably merge X LZC with conversion
// cout the number of leading zeros
if (`IDIV_ON_FPU) begin if (`IDIV_ON_FPU) begin
logic signedDiv; logic signedDiv;
logic AsE, BsE, ALTBE, NegQuotE; logic AsE, BsE, ALTBE, NegQuotE;
@ -72,6 +66,8 @@ module fdivsqrtpreproc (
logic [`XLEN-1:0] PosA, PosB; logic [`XLEN-1:0] PosA, PosB;
logic [`DIVBLEN:0] ZeroDiff, IntBits; logic [`DIVBLEN:0] ZeroDiff, IntBits;
logic [`LOGRK-1:0] RightShiftX; logic [`LOGRK-1:0] RightShiftX;
logic [`DIVBLEN:0] pPlusr, pPrCeil, p;
logic [`LOGRK-1:0] pPrTrunc;
// Extract inputs, signs, zero, depending on W64 mode if applicable // Extract inputs, signs, zero, depending on W64 mode if applicable
assign signedDiv = ~Funct3E[0]; assign signedDiv = ~Funct3E[0];
@ -149,16 +145,15 @@ module fdivsqrtpreproc (
assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
// append leading 1 (for nonzero inputs) and zero-extend // append leading 1 (for nonzero inputs) and zero-extend
assign SqrtX = (Xe[0]^ell[0]) ? {1'b0, ~NumZeroE, XPreproc[`DIVb-1:1]} : {~NumZeroE, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF assign PreSqrtX = (Xe[0]^ell[0]) ? {1'b0, ~NumZeroE, XPreproc[`DIVb-1:1]} : {~NumZeroE, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF
assign DivX = {3'b000, ~NumZeroE, XPreproc}; assign DivX = {3'b000, ~NumZeroE, XPreproc};
// Sqrt is initialized after a first step of R(X-1), which depends on Radix
// *** explain why X is shifted between radices (initial assignment of WS=RX) if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
if (`RADIX == 2) assign PreShiftX = Sqrt ? {3'b111, SqrtX} : DivX; else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
else assign PreShiftX = Sqrt ? {2'b11, SqrtX, 1'b0} : DivX; assign PreShiftX = Sqrt ? SqrtX : DivX;
// Floating-point exponent // Floating-point exponent
fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE)); fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
endmodule endmodule