From 4f40bd07c37c7b1c538724f6e840882fafc4f494 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 29 Aug 2022 17:04:53 -0500 Subject: [PATCH] Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. --- pipelined/src/ifu/ifu.sv | 6 ++++-- pipelined/src/lsu/lsu.sv | 5 +++-- pipelined/src/wally/wallypipelinedcore.sv | 23 +++++++++++++++++++++++ 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 65e42a61..9ed92be8 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -248,7 +248,9 @@ module ifu ( .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); end else begin : passthrough assign IFUHADDR = PCPF; - flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0])); + logic CaptureEn; + + flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); /* -----\/----- EXCLUDED -----\/----- busfsm #(LOGBWPL) busfsm( @@ -258,7 +260,7 @@ module ifu ( .HTRANS(IFUHTRANS), .BusCommitted()); -----/\----- EXCLUDED -----/\----- */ - AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), + AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn, .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); assign IFUHBURST = 3'b0; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index abd4afc5..9a089def 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -272,10 +272,11 @@ module lsu ( mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(LSUHWDATA)); end else begin : passthrough // just needs a register to hold the value from the bus + logic CaptureEn; assign LSUHADDR = LSUPAdrM; assign LSUHSIZE = LSUFunct3M; - flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM)); + flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM)); assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0]; /* -----\/----- EXCLUDED -----\/----- @@ -287,7 +288,7 @@ module lsu ( -----/\----- EXCLUDED -----/\----- */ AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), - .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), + .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE)); assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c781d843..a3481430 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -294,6 +294,7 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories if(`BUS) begin : ebu +/* -----\/----- EXCLUDED -----\/----- ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), @@ -320,6 +321,28 @@ module wallypipelinedcore ( .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK); + -----/\----- EXCLUDED -----/\----- */ + + ahbmultimanager ebu(// IFU connections + .clk, .reset, + .IFUHADDR, + .IFUHBURST, + .IFUHTRANS, + .IFUHREADY, + + // Signals from Data Cache + .LSUHADDR, + .LSUHWDATA, + .LSUHSIZE, + .LSUHBURST, + .LSUHTRANS, + .LSUHWRITE, + .LSUHREADY, + + .HREADY, .HRESP, .HCLK, .HRESETn, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, + .HPROT, .HTRANS, .HMASTLOCK); + end