forked from Github_Repos/cvw
More unused signal cleanup
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@ -212,25 +212,12 @@ module fpu (
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.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
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.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
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.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
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.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
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// convert from signle to double and vice versa
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// other FP execution units
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cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
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cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
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// compare unit
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// - computation is done in one stage
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// - writes to FP file durring min/max instructions
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// - other comparisons write a 1 or 0 to the integer register
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fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE,
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fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE,
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.XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
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.XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
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fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE);
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// sign injection unit
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fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
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fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
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.SgnResE);
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// classify
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fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE,
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.XSNaNE, .ClassResE);
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// Convert
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fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
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fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
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.CvtResE, .CvtFlgE);
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.CvtResE, .CvtFlgE);
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@ -3,7 +3,6 @@
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module fsgn (
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module fsgn (
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input logic XSgnE, YSgnE, // X and Y sign bits
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input logic XSgnE, YSgnE, // X and Y sign bits
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input logic [63:0] FSrcXE, // X
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input logic [63:0] FSrcXE, // X
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input logic XExpMaxE, // max possible exponent (all ones)
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input logic FmtE, // precision 1 = double 0 = single
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input logic FmtE, // precision 1 = double 0 = single
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input logic [1:0] SgnOpCodeE, // operation control
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input logic [1:0] SgnOpCodeE, // operation control
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output logic [63:0] SgnResE // result
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output logic [63:0] SgnResE // result
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@ -77,11 +77,7 @@ module datapath (
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// Execute stage signals
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// Execute stage signals
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logic [`XLEN-1:0] R1E, R2E;
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logic [`XLEN-1:0] R1E, R2E;
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logic [`XLEN-1:0] ExtImmE;
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logic [`XLEN-1:0] ExtImmE;
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// logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAE2, SrcBE2;
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logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
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logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
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// Memory stage signals
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// Memory stage signals
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] IEUResultM;
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@ -212,7 +212,7 @@ module privileged (
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
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// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
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// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
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trap trap(.clk, .reset,
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trap trap(.reset,
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.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
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.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
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@ -32,7 +32,6 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module trap (
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module trap (
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input logic clk,
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input logic reset,
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input logic reset,
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(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
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(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
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(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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