diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index 47f29a19..5149b05e 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -212,25 +212,12 @@ module fpu (
          .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
          .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
 
-   // convert from signle to double and vice versa
+   // other FP execution units
    cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
-
-   // compare unit
-   //    - computation is done in one stage
-   //    - writes to FP file durring min/max instructions
-   //    - other comparisons write a 1 or 0 to the integer register
    fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, 
             .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
-
-   // sign injection unit
-   fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
-    .SgnResE);
-
-   // classify
-   fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, 
-         .XSNaNE, .ClassResE);
-
-   // Convert
+   fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE);
+   fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
    fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
    .CvtResE, .CvtFlgE);
 
diff --git a/pipelined/src/fpu/fsgn.sv b/pipelined/src/fpu/fsgn.sv
index efe6ece3..b95fd078 100755
--- a/pipelined/src/fpu/fsgn.sv
+++ b/pipelined/src/fpu/fsgn.sv
@@ -3,7 +3,6 @@
 module fsgn (  
 	input logic        	XSgnE, YSgnE,	// X and Y sign bits
 	input logic [63:0] 	FSrcXE,			// X
-	input logic			XExpMaxE,		// max possible exponent (all ones)
 	input logic 		FmtE,			// precision 1 = double 0 = single
 	input  logic [1:0]  SgnOpCodeE,		// operation control
 	output logic [63:0] SgnResE		// result
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 8178f165..90b5f033 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -77,11 +77,7 @@ module datapath (
   // Execute stage signals
   logic [`XLEN-1:0] R1E, R2E;
   logic [`XLEN-1:0] ExtImmE;
-
-  // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
   logic [`XLEN-1:0] SrcAE, SrcBE;
-  logic [`XLEN-1:0] SrcAE2, SrcBE2;
-
   logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
   // Memory stage signals
   logic [`XLEN-1:0] IEUResultM;
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 05a98eb1..7d58228b 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -212,7 +212,7 @@ module privileged (
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
   // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
-  trap trap(.clk, .reset,
+  trap trap(.reset,
             .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
             .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
             .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index 1b8e562b..611378de 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -32,8 +32,7 @@
 `include "wally-config.vh"
 
 module trap (
-  input logic 		   clk,
-  input logic 		   reset, 
+   input logic 		   reset, 
   (* mark_debug = "true" *) input logic 		   InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
   (* mark_debug = "true" *) input logic 		   BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
   (* mark_debug = "true" *) input logic 		   LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,