forked from Github_Repos/cvw
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
This commit is contained in:
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f2a6e8c6cf
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@ -86,3 +86,6 @@
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/* verilator lint_off STMTDLY */
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
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1024
wally-pipelined/config/coremark/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/coremark/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
@ -88,3 +88,6 @@
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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/* verilator lint_off PINCONNECTEMPTY */
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`define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/coremark/BTBPredictor.txt"
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1024
wally-pipelined/config/rv32ic/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv32ic/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
@ -84,3 +84,6 @@
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/* verilator lint_off STMTDLY */
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
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1024
wally-pipelined/config/rv64ic/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv64ic/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
@ -87,3 +87,6 @@
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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/* verilator lint_off PINCONNECTEMPTY */
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`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
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1024
wally-pipelined/config/rv64icfd/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv64icfd/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
@ -87,3 +87,6 @@
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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/* verilator lint_off PINCONNECTEMPTY */
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`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
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@ -31,16 +31,9 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc=+/testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench_busybear -o workopt
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vopt work.testbench_busybear -o workopt
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vsim workopt -suppress 8852,12070
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vsim workopt -suppress 8852,12070
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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run -all
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run -all
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quit
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quit
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@ -34,13 +34,6 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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vopt +acc work.testbench_busybear -o workopt
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vopt +acc work.testbench_busybear -o workopt
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vsim workopt -suppress 8852,12070
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vsim workopt -suppress 8852,12070
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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view wave
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@ -35,14 +35,6 @@ vlog +incdir+../config/coremark ../testbench/testbench-coremark.sv ../src/*/*.sv
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vopt +acc work.testbench -o workopt
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vopt +acc work.testbench -o workopt
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vsim workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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view wave
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-- display input and output signals as hexidecimal values
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-- display input and output signals as hexidecimal values
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@ -38,13 +38,6 @@ switch $argc {
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vopt +acc work.testbench -o workopt
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vopt +acc work.testbench -o workopt
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vsim workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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view wave
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do wally-peripherals-signals.do
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do wally-peripherals-signals.do
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@ -31,11 +31,8 @@ vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc=+/testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench -o workopt
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vopt work.testbench -o workopt
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vsim workopt
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vsim workopt
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
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run -all
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run -all
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quit
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quit
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@ -35,16 +35,8 @@ switch $argc {
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}
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}
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc=+/testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench -o workopt
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vopt work.testbench -o workopt
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vsim workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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run -all
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run -all
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quit
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quit
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@ -38,13 +38,6 @@ switch $argc {
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vopt +acc -gDEBUG=1 work.testbench -o workopt
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vopt +acc -gDEBUG=1 work.testbench -o workopt
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vsim workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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do wave.do
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do wave.do
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add log -r /*
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add log -r /*
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@ -38,13 +38,6 @@ switch $argc {
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vopt +acc work.testbench -o workopt
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vopt +acc work.testbench -o workopt
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vsim workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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view wave
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@ -471,6 +471,12 @@ string tests32i[] = {
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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.ProgramLabelMapFile(ProgramLabelMapFile));
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end
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end
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// initialize the branch predictor
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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end
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endmodule
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endmodule
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