Merge pull request #30 from davidharrishmc/dev

cleanup

addins/imperas-riscv-tests

@@ -1 +0,0 @@
-/opt/riscv/imperas-riscv-tests/

examples/C/sum/Makefile

@@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
 	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
+	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \

pipelined/src/ifu/brpred/bpred.sv

@@ -49,7 +49,7 @@ module bpred (
   // Branch and jump outcome
   input  logic             PCSrcE,                    // Executation stage branch is taken
   input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [`XLEN-1:0]  dPCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
   // Report branch prediction status
@@ -58,7 +58,7 @@ module bpred (
   output logic             BTBPredPCWrongM,           // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
   output logic             PredictionInstrClassWrongM // Class prediction is wrong
-   );
+);
 
   logic                     BTBValidF;
   logic [1:0]               DirPredictionF;