diff --git a/addins/imperas-riscv-tests b/addins/imperas-riscv-tests
deleted file mode 120000
index c3f365a4..00000000
--- a/addins/imperas-riscv-tests
+++ /dev/null
@@ -1 +0,0 @@
-/opt/riscv/imperas-riscv-tests/
\ No newline at end of file
diff --git a/examples/C/sum/Makefile b/examples/C/sum/Makefile
index 7c21cce2..a302309f 100644
--- a/examples/C/sum/Makefile
+++ b/examples/C/sum/Makefile
@@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
 	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
+	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 9c5efe30..4e1ada3c 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -29,36 +29,36 @@
 `include "wally-config.vh"
 
 module bpred (
-   input logic              clk, reset,
-   input logic              StallF, StallD, StallE, StallM, StallW,
-   input logic              FlushD, FlushE, FlushM, FlushW,
-   // Fetch stage
-   // the prediction
-   input logic [31:0]       InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-   input logic [`XLEN-1:0]  PCNextF,                   // Next Fetch Address
-   input logic [`XLEN-1:0]  PCPlus2or4F,               // PCF+2/4
-   output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
-   output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
+  input  logic             clk, reset,
+  input  logic             StallF, StallD, StallE, StallM, StallW,
+  input  logic             FlushD, FlushE, FlushM, FlushW,
+  // Fetch stage
+  // the prediction
+  input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
+  input  logic [`XLEN-1:0] PCNextF,                   // Next Fetch Address
+  input  logic [`XLEN-1:0] PCPlus2or4F,               // PCF+2/4
+  output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
+  output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
 
-   // Update Predictor
-   input logic [`XLEN-1:0]  PCF,                       // Fetch stage instruction address
-   input logic [`XLEN-1:0]  PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-   input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
-   input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
+  // Update Predictor
+  input  logic [`XLEN-1:0] PCF,                       // Fetch stage instruction address
+  input  logic [`XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+  input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
+  input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
 
-   // Branch and jump outcome
-   input logic              PCSrcE,                    // Executation stage branch is taken
-   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
-   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
-   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  // Branch and jump outcome
+  input  logic             PCSrcE,                    // Executation stage branch is taken
+  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
+  input  logic [`XLEN-1:0]  dPCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
-   // Report branch prediction status
-   output logic             BPPredWrongE,              // Prediction is wrong
-   output logic             DirPredictionWrongM,       // Prediction direction is wrong
-   output logic             BTBPredPCWrongM,           // Prediction target wrong
-   output logic             RASPredPCWrongM,           // RAS prediction is wrong
-   output logic             PredictionInstrClassWrongM // Class prediction is wrong
-   );
+  // Report branch prediction status
+  output logic             BPPredWrongE,              // Prediction is wrong
+  output logic             DirPredictionWrongM,       // Prediction direction is wrong
+  output logic             BTBPredPCWrongM,           // Prediction target wrong
+  output logic             RASPredPCWrongM,           // RAS prediction is wrong
+  output logic             PredictionInstrClassWrongM // Class prediction is wrong
+);
 
   logic                     BTBValidF;
   logic [1:0]               DirPredictionF;