From 8854532a79b8ad060454391765e52a7eaa318505 Mon Sep 17 00:00:00 2001 From: Abe Date: Tue, 6 Jul 2021 12:37:58 -0400 Subject: [PATCH 1/2] Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) --- wally-pipelined/src/privileged/csrm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 29cc482f..4cba40c9 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -137,7 +137,7 @@ module csrm #(parameter else flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTEREN_REGW); endgenerate - flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTINHIBIT_REGW); + flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'h0, MCOUNTINHIBIT_REGW); // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop From d3dd70e3e678c95df43faac7b1d37e68259dbcf9 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 6 Jul 2021 14:33:52 -0400 Subject: [PATCH 2/2] more completely uncomment MMU tests to make sim wally work --- wally-pipelined/testbench/testbench-imperas.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 33bafaf5..a4daf7f3 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -44,14 +44,14 @@ module testbench(); logic [31:0] InstrW; logic [`XLEN-1:0] meminit; - string tests32mmu[] = '{ + //string tests32mmu[] = '{ //"rv32mmu/WALLY-MMU-SV32", "3000" - }; + // }; - string tests64mmu[] = '{ + //string tests64mmu[] = '{ //"rv64mmu/WALLY-MMU-SV48", "3000", //"rv64mmu/WALLY-MMU-SV39", "3000" - }; + //}; string tests32f[] = '{ @@ -540,7 +540,7 @@ string tests32f[] = '{ else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; if (`A_SUPPORTED) tests = {tests, tests64a}; - if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; + //if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; end @@ -558,7 +558,7 @@ string tests32f[] = '{ if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; if (`F_SUPPORTED) tests = {tests32f, tests}; if (`A_SUPPORTED) tests = {tests, tests32a}; - if (`MEM_VIRTMEM) tests = {tests, tests32mmu}; + //if (`MEM_VIRTMEM) tests = {tests, tests32mmu}; end end end