From 41052178ce3e21f2afc4ae27afe0da82a83a3f34 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 31 Dec 2021 07:11:03 +0000
Subject: [PATCH] Removed .* from CSRs

---
 wally-pipelined/src/privileged/csr.sv        | 50 +++++++++++++++++---
 wally-pipelined/src/privileged/privileged.sv |  2 -
 2 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index 5ca76eb1..2e5d8daf 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -112,13 +112,49 @@ module csr #(parameter
   assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
   assign CSRUWriteM = CSRWriteM;  
 
-  csri  csri(.*);
-  csrsr csrsr(.*);
-  csrc  counters(.*);
-  csrm  csrm(.*); // Machine Mode CSRs
-  csrs  csrs(.*);
-  csrn  csrn(.CSRNWriteM(CSRUWriteM), .*);  // User Mode Exception Registers
-  csru  csru(.*); // Floating Point Flags are part of User MOde
+  csri  csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
+             .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
+             .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
+  csrsr csrsr(.clk, .reset, .StallW,
+              .WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM, 
+              .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
+              .mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
+              .MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW,
+              .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
+              .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);
+  csrc  counters(.clk, .reset,
+              .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,   
+              .InstrValidM, .LoadStallD, .CSRMWriteM,
+              .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+              .InstrClassM, .DCacheMiss, .DCacheAccess,
+              .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
+              .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
+              .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
+  csrm  csrm(.clk, .reset, .StallW,
+              .CSRMWriteM, .MTrapM, .CSRAdrM,
+              .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, 
+              .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
+              .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, 
+              .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+              .MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
+              .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
+  csrs  csrs(.clk, .reset,  .StallW,
+              .CSRSWriteM, .STrapM, .CSRAdrM,
+              .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
+              .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
+              .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
+              .SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW, 
+              .SATP_REGW, .SIP_REGW, .SIE_REGW,
+              .WriteSSTATUSM, .IllegalCSRSAccessM);
+  csrn  csrn(.clk, .reset, .StallW,
+              .CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
+              .NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW, 
+              .CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW, 
+              .UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
+  csru  csru(.clk, .reset, .StallW,
+              .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,  
+              .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
+              .IllegalCSRUAccessM);
 
   // merge CSR Reads
   assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; 
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index e5711393..6adaa249 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -153,7 +153,6 @@ module privileged (
   ///////////////////////////////////////////
   // Control and Status Registers
   ///////////////////////////////////////////
-  //csr csr(.*);
   csr csr(.clk, .reset,
           .FlushE, .FlushM, .FlushW,
           .StallE, .StallM, .StallW,
@@ -216,7 +215,6 @@ module privileged (
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
   // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
-  //trap trap(.*);
   trap trap(.clk, .reset,
             .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
             .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,