Modified plic and uart to remove async reset. This removes vivado critical warning.

src/uncore/plic_apb.sv

@@ -97,7 +97,7 @@ module plic_apb (
   // ==================
   // Register Interface
   // ==================
-  always @(posedge PCLK,negedge PRESETn) begin
+  always @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
       intPriority   <= #1 {`N{3'b0}};

src/uncore/uartPC16550D.sv

@@ -290,7 +290,7 @@ module uartPC16550D(
   assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
 
   // receive FIFO and register
-  always_ff @(posedge PCLK, negedge PRESETn)
+  always_ff @(posedge PCLK)
     if (~PRESETn) begin
       rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
     end else begin