diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8132fa37..7231f609 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -97,7 +97,7 @@ module plic_apb ( // ================== // Register Interface // ================== - always @(posedge PCLK,negedge PRESETn) begin + always @(posedge PCLK) begin // resetting if (~PRESETn) begin intPriority <= #1 {`N{3'b0}}; diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index b33c4962..a2255af5 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -290,7 +290,7 @@ module uartPC16550D( assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time // receive FIFO and register - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; end else begin